Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Features
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Description
The device consists of four independent channels of
codec and digital signal processing functions on one
chip. In addition to the classic A-to-D and D-to-A con-
version, each channel provides termination imped-
ance synthesis and a hybrid balance network.
The device is controlled by a serial microprocessor
interface, and a series of bidirectional I/O leads are
provided so that this control mechanism can be uti-
lized to operate the battery feed device, ringing volt-
age switches, etc. Common data and clock paths can
be shared over any number of devices. All the filter
coefficients, signal processing, SLIC, and test fea-
tures are accessible through this interface. This
serial interface can be operated at speeds up to
16 Mbits/s.
The choice of a PCM bus is also programmable, with
any channel capable of being assigned to any time
slot. The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in two packages.
The T8538B 64-pin TQFP features five data latches
per channel and the 100-pin TQFP features six data
latches per channel.
Both devices are pin-compatible with the T8536B 5 V
quad programmable codecs.
3.3 V operation
Per-channel programmable gains, equalization,
termination impedance, and hybrid balance
Programmable
µ-law,
linear, or A-law modes:
— Up to 256 time slots per frame
— Supports PCM data rates of 512 kbits/s to
16.384 Mbits/s
— Double-clock mode timing compatible with
ISDN standard interfaces
Fully programmable time-slot assignment with bit
offset
Analog and digital loopback test modes
Serial microprocessor interface:
— Normal and byte-by-byte control modes
— Fast scan mode
Six bidirectional control leads per channel, for
SLIC and line card function control
Differential analog output:
— Mates directly to SLICs, eliminating external
components
Sigma-delta converters with dither noise reduction
Quad design to minimize package count on dense
line card applications
Meets or exceeds ITU-T G.711—G.712 and rele-
vant
Telcordia Technologies
TM
requirements
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T8538B Quad Programmable Codec
Preliminary Data Sheet
August 2001
Table of Contents
Contents
Page
Figure 8. Write Operation, Byte-by-Byte Mode
(Gapped DCLK)......................................... 13
Figure 9. Write Operation, Byte-by-Byte Mode
(Continuous DCLK) ................................... 13
Figure 10. Read Operation, Normal Mode
(Continuous DCLK) ................................. 14
Figure 11. Read Operation, Normal Mode
(Gapped DCLK) ...................................... 15
Figure 12. Read Operation, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 15
Figure 13. Read Operation, Byte-by-Byte Mode
(Continuous DCLK) ................................. 16
Figure 14. Fast Scan, Normal Mode
(Continuous DCLK) ................................. 17
Figure 15. Fast Scan, Normal Mode (Gapped
DCLK) ..................................................... 18
Figure 16. Fast Scan, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 18
Figure 17. Fast Scan, Byte-by-Byte Mode
(Continuous DCLK) ................................. 19
Figure 18. Hardware Reset Procedure..................... 19
Figure 19. Internal Signal Processing....................... 22
Figure 20. Serial Interface Timing, Normal Mode
(One Byte Transfer and Continuous
DCLK Shown) ......................................... 32
Figure 21. Byte-by-Byte Mode Timing
(Gapped DCLK Shown) .......................... 32
Figure 22. Single-Clocking Mode (TXBITOFF = 0,
RXBITOFF = 0, PCMCTRL2 = 0x00) ...... 34
Figure 23. Single-Clocking Mode (TXBITOFF = 1,
RXBITOFF = 2, PCMCTRL2 = 0x01) ...... 34
Figure 24. Double-Clocking Mode (RXBITOFF =
0x20, PCMCTRL2 = 0x00) ...................... 36
Figure 25. POTS Interface........................................ 41
Features ......................................................................1
Description...................................................................1
General Description.....................................................3
Pin Information ............................................................5
Functional Description .................................................9
Clocking Considerations ...........................................9
The Control Interface ................................................9
Modes ....................................................................9
Protocol ................................................................10
Write Command ...................................................12
Read Command ...................................................14
Fast Scan Mode ...................................................17
Write All Channels................................................19
Reset Functionality .................................................19
Memory Control Mapping .....................................20
Standby Mode.........................................................20
Test Capabilities .....................................................20
SLIC Control Capabilities ........................................21
Suggested Initialization Procedures........................21
Signal Processing ...................................................22
Absolute Maximum Ratings.......................................22
Operating Ranges .....................................................23
Handling Precautions ................................................23
Electrical Characteristics ...........................................24
dc Characteristics ...................................................24
Analog Interface......................................................25
Gain and Dynamic Range .......................................26
Noise Characteristics ..............................................28
Distortion and Group Delay.....................................29
Crosstalk .................................................................30
Timing Characteristics ...............................................31
Control Interface Timing..........................................31
Serial Control Port Timing ....................................31
Normal Mode........................................................32
Byte-by-Byte Mode...............................................32
PCM Interface Timing .............................................33
Single-Clocking Mode ..........................................33
Double-Clocking Mode.........................................35
Software Interface .....................................................37
Applications ...............................................................41
Outline Diagrams.......................................................42
100-Pin TQFP .........................................................42
64-Pin TQFP ...........................................................43
Ordering Information..................................................44
Tables
Page
Figures
Page
Figure 1. Functional Block Diagram, Each Section .....3
Figure 2. 100-Pin TQFP Pin Diagram..........................5
Figure 3. 64-Pin TQFP Pin Diagram............................7
Figure 4. Command Frame Format, Master to Slave,
Read or Write Commands..........................11
Figure 5. Command Frame Format, Slave to Master,
Read Commands .......................................11
Figure 6. Write Operation, Normal Mode
(Continuous DCLK) ....................................12
Figure 7. Write Operation, Normal Mode (Gapped
DCLK) ........................................................12
2
Table 1. Pin Assignments, 100-Pin TQFP,
Per-Channel Functions................................. 5
Table 2. Pin Assignments, 100-Pin TQFP,
Common Functions ...................................... 6
Table 3. Pin Assignments, 64-Pin TQFP,
Per-Channel Functions................................. 7
Table 4. Pin Assignments, 64-Pin TQFP,
Common Functions ...................................... 8
Table 5. Bit Assignments for Fast Scan Mode ......... 17
Table 6. dc Characteristics ....................................... 24
Table 7. Analog Interface ......................................... 25
Table 8. Power Dissipation....................................... 25
Table 9. Gain and Dynamic Range .......................... 26
Table 10. Per-Channel Noise Characteristics .......... 28
Table 11. Distortion and Group Delay ...................... 29
Table 12. Crosstalk................................................... 30
Table 13. Serial Control Port Timing ........................ 31
Table 14. PCM Interface Timing: Single-Clocking
Mode ........................................................ 33
Table 15. PCM Interface Timing: Double-Clocking
Mode ........................................................ 35
Table 16. Memory Mapping...................................... 37
Table 17. Control Bit Definition................................. 38
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
General Description
Refer to Figure 1 for the following discussion.
ANALOG
GAIN
A/D
CONVERTER
DIGITAL
LOOPBACK 2
ANALOG
LOOPBACK 1
DIGITAL
LOOPBACK 3
ANALOG
LOOPBACK 2
DIGITAL
LOOPBACK 1
DIGITAL GAIN
(GAIN TRANSFER)
PER
CHANNEL
18
COMMON
DX0
DX1
TSX0
TSX1
TO/FROM
PCM BUS
POWER AND
GROUND
VF
X
In
TO/FROM
SLIC
TERMINATION
IMPEDANCE
HYBRID
BALANCE
NETWORK
µ-LAW
OR
A-LAW
CONVERSION
PCM BUS
INTERFACE
VF
R
OPn
VF
R
ONn
D/A
CONVERTER
ANALOG
BUFFER
DIGITAL GAIN
(GAIN TRANSFER)
CONTROL AND DATA SIGNALS
DR0
DR1
FS
BCLK
SLIC
CONTROL LATCHES
5 OR 6
PER
CHANNEL
MICROPROCESSOR CONTROL
FREQUENCY
SYNTHESIZER
COMMON
4
RST
SERIAL
CONTROL
INTERFACE
5-8125CF
Figure 1. Functional Block Diagram, Each Section
This device performs virtually all the signal processing
functions associated with a central office line termina-
tion. Functionality includes line termination impedance
synthesis, fixed hybrid balance impedance synthesis,
and level conversion both in the analog sense to
accommodate various subscriber line interface circuits
(SLICs) and in the digital sense for adjustment of the
levels on the PCM bus. In general, the termination
impedance synthesis generates the equivalent of a cir-
cuit with the parallel combination of a capacitor and a
resistor in series with a resistor or the parallel combina-
tion of a resistor and the series combination of a resis-
tor and capacitor. These general forms of impedance
characteristic will satisfy most of the requirements
specified throughout the world. Programmable selec-
tion of either
µ-law
or A-law encoding further aids
worldwide deployment. All coefficients used in the filter-
ing algorithms can be computed off-line in advance and
downloaded to the device at the time of powerup. All
signal processing is contained within the device, and
there are only three interfaces of consequence to the
system designer: the SLIC interface, the PCM inter-
face, and the control interface.
The SLIC interface is designed to be flexible and con-
venient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, few external components
are required in the interface.
Agere Systems Inc.
3
T8538B Quad Programmable Codec
Preliminary Data Sheet
August 2001
The microprocessor control interface is a serial inter-
face that uses the classical chip select type of opera-
tion. The interface controls the device by writing or
reading various internal addresses. The command set
consists of simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel.
There are several test modes included to facilitate con-
firmation of correct operation. In the signal path, two
analog and three digital loopback tests are available,
while in the microprocessor interface, there is a write/
read test mode that tests the operation of the memory.
Use of external test access switches allows a complete
test of the signal path through the line card so that cor-
rect operation of various operational modes can be ver-
ified.
General Description
(continued)
The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum 16.384 Mbits/s rate to accom-
modate a maximum 256 time slots. Separate pins
are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure for all four channels. The interface will count
8 bits per time slot and insert or read the data for each
channel as programmed. Lower speeds of the PCM
bus are allowed. The PCM clock must be synchronous
with the frame strobe signal.
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Agere Systems Inc.
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