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IDT70V7399S200BF

Description
HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
File Size291KB,22 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

IDT70V7399S200BF Overview

HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 3.3V 128K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
x
IDT70V7399S
x
x
x
x
x
x
128K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
64 independent 2K x 18 banks
– 2 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6 (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
x
x
x
x
x
x
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 144-pin Thin Quad Flatpack (TQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
144-pin TQFP package.
Functional Block Diagram
PL/FT
L
OPT
L
CLK
L
ADS
L
CNTEN
L
REPEAT
L
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
PL/FT
R
OPT
R
CLK
R
ADS
R
CNTEN
R
REPEAT
R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
MUX
2Kx18
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
I/O
0L-17L
I/O
CONTROL
MUX
2Kx18
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
0R-17R
A
10L
A
0L
BA
5L
BA
4L
BA
3L
BA
2L
BA
1L
BA
0L
ADDRESS
DECODE
ADDRESS
DECODE
A
10R
A
0R
BA
5R
BA
4R
BA
3R
BA
2R
BA
1R
BA
0R
BANK
DECODE
MUX
2Kx18
MEMORY
ARRAY
(BANK 63)
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
MUX
,
TDI
TDO
JTAG
TMS
TCK
TRST
5630 drw 01
DECEMBER 2002
1
DSC 5630/6
©2002 Integrated Device Technology, Inc.
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