IDT71V2548S133BQ datasheet, PDF

Datasheet> All Categories > IDT71V2548S133BQ

Preview

IDT71V2548S133BQ: Description128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs; File Size513KB，28 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet View All

IDT71V2548S133BQ Overview

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

Preview

Download Datasheet

View All

128K x 36, 256K x 18

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

IDT71V2546S

IDT71V2548S

IDT71V2546SA

IDT71V2548SA

Features

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 150 MHz

(3.8 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (V

DDQ)

Optional Boundary Scan JTAG Interface (IEEE1149.1

complaint)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array

Description

The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus cycles

when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT

, or Zero Bus

Turnaround.

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2546/48 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to

be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

The IDT71V2546/48 has an on-chip burst counter. In the burst mode,

the IDT71V2546/48 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO

input pin. The

LBO

pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2546/48 SRAMs utilize IDT's latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

Static

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

MAY 2002

DSC-5294/03

5294 tbl 01

Recommended Resources

Working principle of single touch mode light switch

Sound speed measurement circuit

PTC three-phase asynchronous motor protection circuit three

Hybrid Power Amplifier 04

Power outage emergency lights (2)

X63W universal lifting table milling machine electrical schematic circuit (3) circuit when the worktable is forward and the lifting table is downward

ADC12: The MCU is 430F5438, ADC12 is on A0/A7, ADCMEMER0 takes the value of A0, and ADCMEMER1 takes the value of A7; Then the main problem is that these two channels actually interfere with each other; Pheno...; shushu Microcontroller MCU

Problems after installing the PB5.0 patch: After I installed the PB5.0 patch, built .net2.0, and generated nk.bin, it started automatically after installation using the HyperTerminal. However, after shutting down the computer and restarting it...; whatseal Embedded System

Microchip live broadcast [How to protect your IP in cloud service connection] has ended: Currently, the rapid development of various applications and businesses enabled by cloud services has generated a large number of cloud service connections. This means that your IP is facing greater a...; EEWORLD社区 RF/Wirelessly

I'm looking for a Protel diagram of a tracking and obstacle avoidance car using STC89C52, L293D, TCRT5000, and LM339.: As title...; 381104682 MCU

Anyone studying electronics? Join group 45777681: Anyone studying electronics? Join group 45777681 to play together...; zhuzhanf MCU

Selection of solder paste (SMT patch): [i=s]This post was last edited by qwqwqw2088 on 2017-6-18 18:23[/i] [backcolor=rgb(255,255,255)] Solder paste is the core material in SMT technology. If you are not particularly clear about the detail...; qwqwqw2088 Analogue and Mixed Signal

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components