EQVE12C1C1H-112.640M datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> EQVE12C1C1H-112.640M

EQVE12C1C1H-112.640M: DescriptionLVDS, Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD); CategoryPassive components oscillator; File Size961KB，7 Pages; ManufacturerECLIPTEK; Websitehttp://www.ecliptek.com; Environmental Compliance

Download Datasheet Parametric Compare View All

EQVE12C1C1H-112.640M Overview

LVDS, Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

EQVE12C1C1H-112.640M Parametric

Parameter Name	Attribute value
Brand Name	Ecliptek
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ECLIPTEK
Parts packaging code	SMD 5.0mm x 7.0mm
package instruction	SMD, 6 PIN
Contacts	6
Manufacturer packaging code	SMD 5.0mm x 7.0mm
Reach Compliance Code	compli
Other features	ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; BULK; TAPE
Maximum control voltage	2.75 V
Minimum control voltage
maximum descent time	0.5 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	30 ppm
frequency stability	50%
JESD-609 code	e4
linearity	10%
Installation features	SURFACE MOUNT
Nominal operating frequency	112.64 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
Output load	100 OHM
physical size	7.0mm x 5.0mm x 1.8mm
longest rise time	0.5 ns
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	60/40 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

EQVE12C1C1H-112.640M

REGULATORY COMPLIANCE

2011/65 +

2015/863

(Data Sheet downloaded on Aug 31, 2020)

191 SVHC

ITEM DESCRIPTION

Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount

(SMD) 112.640MHz ±50ppm -40°C to +85°C

ELECTRICAL SPECIFICATIONS

Nominal Frequency

Frequency Tolerance/Stability

Aging at 25°C

Operating Temperature Range

Supply Voltage

Input Current

Output Voltage Logic High (Voh)

Output Voltage Logic Low (Vol)

Differential Output Error (dVod)

Differential Output Voltage (Vod)

Offset Voltage (Vos)

Rise/Fall Time

Duty Cycle

Offset Error (dVos)

Load Drive Capability

Output Logic Type

Absolute Pull Range

112.640MHz

±50ppm Maximum (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating

Temperature Range, Supply Voltage Change and Output Load Change)

±2ppm Maximum First Year, ±10ppm/10 Years Maximum

-40°C to +85°C

2.5Vdc ±5%

25mA Maximum

1.425Vdc Typical

1.075Vdc Typical

50mVdc Maximum

200mVdc Minimum, 350mVdc Typical, 454mVdc Maximum

1.125V Minimum, 1.250V Typical, 1.375V Maximum

500pSec Maximum (Measured at 20% to 80% of Waveform)

50 ±10(%) (Measured at 50% of Waveform)

50mVdc Maximum

100 Ohms Between Output and Complementary Output

LVDS

±30ppm Minimum (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating

Temperature Range, Supply Voltage Change, Output Load Change, Shock, Vibration, and 10 Year Aging over the

Control Voltage (Vc))

0.2Vdc to 2.3Vdc (Test Condition for APR)

0.0Vdc to Vdd +0.25Vdc

5% Typical, 10% Maximum

Positive Tranfer Characteristic

10kHz Minimum (Measured at -3dB, Vc = 1.25Vdc)

500kOhms Minimum

10µA Maximum

-57dBc/Hz at 10Hz offset; -86dBc/Hz at 100Hz offset; -114dBc/Hz at 1kHz offset; -121dBc/Hz at 10kHz offset; -

122dBc/Hz at 100kHz offset; -141dBc/Hz at 1MHz offset; -151dBc/Hz at 10MHz offset; -153dBc/Hz at 20MHz offset (All

Values are Typical)

Output Enable (OE)

90% of Vdd Minimum or No Connect to Enable Output and Complementary Output

10% of Vdd Maximum to Disable Output and Complementary Output (High Impedance)

100nSec Maximum

50nSec Maximum

15mA Maximum (Without Load (Pin 2 = Ground))

1.3pSec Maximum (Fj=12kHz to 20MHz (Random))

0.2pSec Typical

Control Voltage

Control Voltage Range

Linearity

Transfer Function

Modulation Bandwidth

Input Impedance

Input Leakage Current

Phase Noise

Output Control Function

Output Control Input Voltage Logic

High (Vih)

Output Control Input Voltage Logic

Low (Vil)

Output Enable Time

Output Disable Time

Output Enable Current

RMS Phase Jitter

Period Jitter (Deterministic)

www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 1 of 7

Ecliptek, LLC

5458 Louie Lane, Reno, NV 89511

1-800-ECLIPTEK or 714.433.1200

EQVE12C1C1H-112.640M Related Products

	EQVE12C1C1H-112.640M	EQVE12C1C1H-112.640M TR
Description	LVDS, Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)	LVDS, Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)
Brand Name	Ecliptek	Ecliptek
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Parts packaging code	SMD 5.0mm x 7.0mm	SMD 5.0mm x 7.0mm
Contacts	6	6
Manufacturer packaging code	SMD 5.0mm x 7.0mm	SMD 5.0mm x 7.0mm
Reach Compliance Code	compli	163
Base Number Matches	1	1

Recommended Resources

Fluorescent lamp electronic ballast circuit 4

Standard frequency shift keying modem circuit with 300 baud speed

Thermistor type thermal conduction gas sensor circuit

pressure regulation control circuit

845E computer motherboard circuit diagram_64

Telephone Busy Indicator Circuit 2

FPGA Encryption Methods: Please download the attachment for FPGA encryption method~~...; rocetech FPGA/CPLD

Step amplifier (low frequency amplification, high frequency pass): How to design an active amplifier that can amplify low-frequency signals while allowing high-frequency signals to pass normally? I made some modifications based on the common-mode amplifier, but the e...; 无垠星空 Analog electronics

Single chip microcomputer and ISA bus Ethernet solution: [b][font=隶书][size=4][color=#800080]Single-Chip Microcomputer and TCP/IP Network[/color][/size][/font][/b] [b][font=隶书][size=4][color=#800080][/color][/size][/font][/b] [size=2] ——[/size][size=4]How do...; songbo MCU

Circuit Diagram: 2OHM1000W power amplifier circuit diagram...; cjx19840106 PCB Design

How to build a wince5.0 development environment with win7 x64 + VS2008: After I installed wince 5.0 sdk, I found the sdk in vs, but there is no simulator. I can't install the simulator even if I download it. It always prompts an error. The most important pb is also missin...; YUZHIZUI Embedded System

ATmega16 prescaler usage problem: In the chip manual, it is described that TC0 and TC1 share a prescaler, but can have different frequency division settings. I would like to ask the seniors who are familiar with 16, how do you underst...; 不见曦月 MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components