EQVE12C2C1H-112.640M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Sep 6, 2020)
191 SVHC
ITEM DESCRIPTION
Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount
(SMD) 112.640MHz ±50ppm -40°C to +85°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Differential Output Error (dVod)
Differential Output Voltage (Vod)
Offset Voltage (Vos)
Rise/Fall Time
Duty Cycle
Offset Error (dVos)
Load Drive Capability
Output Logic Type
Absolute Pull Range
112.640MHz
±50ppm Maximum (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating
Temperature Range, Supply Voltage Change and Output Load Change)
±2ppm Maximum First Year, ±10ppm/10 Years Maximum
-40°C to +85°C
2.5Vdc ±5%
25mA Maximum
1.425Vdc Typical
1.075Vdc Typical
50mVdc Maximum
200mVdc Minimum, 350mVdc Typical, 454mVdc Maximum
1.125V Minimum, 1.250V Typical, 1.375V Maximum
500pSec Maximum (Measured at 20% to 80% of Waveform)
50 ±10(%) (Measured at 50% of Waveform)
50mVdc Maximum
100 Ohms Between Output and Complementary Output
LVDS
±50ppm Minimum (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating
Temperature Range, Supply Voltage Change, Output Load Change, Shock, Vibration, and 10 Year Aging over the
Control Voltage (Vc))
0.2Vdc to 2.3Vdc (Test Condition for APR)
0.0Vdc to Vdd +0.25Vdc
5% Typical, 10% Maximum
Positive Tranfer Characteristic
10kHz Minimum (Measured at -3dB, Vc = 1.25Vdc)
500kOhms Minimum
10µA Maximum
-57dBc/Hz at 10Hz offset; -86dBc/Hz at 100Hz offset; -114dBc/Hz at 1kHz offset; -121dBc/Hz at 10kHz offset; -
122dBc/Hz at 100kHz offset; -141dBc/Hz at 1MHz offset; -151dBc/Hz at 10MHz offset; -153dBc/Hz at 20MHz offset (All
Values are Typical)
Output Enable (OE)
90% of Vdd Minimum or No Connect to Enable Output and Complementary Output
10% of Vdd Maximum to Disable Output and Complementary Output (High Impedance)
100nSec Maximum
50nSec Maximum
15mA Maximum (Without Load (Pin 2 = Ground))
1.3pSec Maximum (Fj=12kHz to 20MHz (Random))
0.2pSec Typical
Control Voltage
Control Voltage Range
Linearity
Transfer Function
Modulation Bandwidth
Input Impedance
Input Leakage Current
Phase Noise
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Output Enable Time
Output Disable Time
Output Enable Current
RMS Phase Jitter
Period Jitter (Deterministic)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQVE12C2C1H-112.640M
ELECTRICAL SPECIFICATIONS CONTINUED
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
Start Up Time
Storage Temperature Range
2pSec Typical
3pSec Maximum
25pSec Maximum
10mSec Maximum
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 2 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQVE12C2C1H-112.640M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
CONNECTION
Control Voltage
Output Enable (OE)
Case/Ground
Output
Complementary Output
Supply Voltage
1.70
MAX
5.00
±0.20
MARKING
ORIENTATION
2.60 ±0.15
1.2 ±0.2
2.54
TYP
5.08
±0.15
6
5
4
1
2
3
1.4
±0.2
2
3
4
5
6
7.00
±0.20
LINE MARKING
1
2
3
ECLIPTEK
112.64M
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.80 (X6)
2.00 (X6)
0.54 (X4)
1.89
All Tolerances are ±0.1
Solder Land
(X6)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 3 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQVE12C2C1H-112.640M
OUTPUT WAVEFORM & TIMING DIAGRAM
V
IH
INPUT
V
IL
CLOCK OUTPUTS
V
OH
80%
50%
20%
V
OL
V
OD
Q
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
V
OS
Q
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 4 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQVE12C2C1H-112.640M
Test Circuit for LVDS Output
Oscilloscope
Frequency
Counter
Current
Meter
Power
Supply
Voltage
Meter
0.01µF
(Note 1)
0.1µF
(Note 1)
Supply
Voltage
(V
DD
)
Probe 2
(Note 2)
Probe 1
(Note 2)
100 Ohms
Complementary
Output
Output Enable
Output
Ground
Control
Voltage
Power
Supply
Voltage
Meter
Switch
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency
ceramic bypass capacitor close (less than 2mm) to the package ground and supply
voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms),
and high bandwidth (>500MHz) passive probe is recommended.
Note 3: Test circuit PCB traces need to be designed for a characteristic line impedance of 50 ohms.
Power
Supply
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 5 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
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