V59C1G01(808/168)QC
HIGH PERFORMANCE 1Gbit DDR2 SDRAM
8 BANKS X 16Mbit X 8 (808)
8 BANKS X 8Mbit X 16 (168)
37
DDR2-533
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
Clock Cycle Time (t
CK5
)
Clock Cycle Time (t
CK6
)
Clock Cycle Time (t
CK7
)
System Frequency (f
CK max
)
5ns
3.75ns
-
-
-
266 MHz
3
DDR2-667
5ns
3.75ns
3ns
-
-
333 MHz
25A
DDR2-800
5ns
3.75ns
3ns
2.5ns
-
400 MHz
25
DDR2-800
5ns
3.75ns
2.5ns
2.5ns
-
400 MHz
19A
DDR2-1066
5ns
3.75ns
3ns
2.5ns
1.875ns
533 MHz
Features
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High speed data transfer rates with system frequency up to
533 MHz
8 internal banks for concurrent operation
4-bit prefetch architecture
Programmable CAS Latency: 3, 4 ,5 , 6 and 7
Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6
Write Latency = Read Latency -1
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 us at -40
o
C
≤
Tcase
≤
85
o
C,
3.9 us at 85
o
C < Tcase
≤
105
o
C
ODT (On-Die Termination)
Weak Strength Data-Output Driver Option
Bidirectional differential Data Strobe (Single-ended data-
strobe is an optional feature)
On-Chip DLL aligns DQ and DQs transitions with CK transi-
tions
DQS can be disabled for single-ended data strobe
Read Data Strobe (RDQS) supported (x8 only)
Differential clock inputs CK and CK
JEDEC Power Supply 1.8V ± 0.1V
VDDQ =1.8V ± 0.1V
Available in 60-ball FBGA for x8 component or 84-ball FBGA
for x16 component
RoHS compliant
PASR Partial Array Self Refresh
tRAS lockout supported
Description
The V59C1G01(808/168)QC is a eight bank DDR DRAM or-
ganized as 8 banks x 16Mbit x 8 (808), or 8 banks x 8Mbit x 16
(168). The V59C1G01(808/168)QC achieves high speed data
transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system
clock.
The chip is designed to comply with the following key DDR2
SDRAM features:(1) posted CAS with additive latency, (2) write
latency = read latency-1, (3) On Die Termination.
All of the control, address, circuits are synchronized with the
positive edge of an externally supplied clock. I/O s are synchro-
nized with a pair of bidirectional strobes (DQS, DQS) in a source
synchronous fashion.
Operating the eight memory banks in an interleaved fashion
allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS latency and
speed grade of the device.
Available Speed Grade
1:
Table
Grade
-37 (DDR2-533)
-3 (DDR2-667)
-25A (DDR2-800)
-25 (DDR2-800)
-19A (DDR2-1066)
CL
4
5
6
5
7
tRCD
4
5
6
5
7
tRP
4
5
6
5
7
Unit
CLK
CLK
CLK
CLK
CLK
Device Usage Chart
Operating
Temperature
Range
0°C
≤
Tc
≤
85°C
-40°C
≤
Tc
≤
95°C
-40°C
≤
Tc
≤
105°C
V59C1G01(808/168)QC Rev.1.5 June 2012
Package Outline
60-ball FBGA
84-ball FBGA
•
•
•
CK Cycle Time (ns)
-37
•
•
•
Power
-19A
•
•
•
-3
•
•
•
-25A
•
•
•
-25
•
•
•
Std.
•
•
•
L
•
•
•
Temperature
Mark
Blank
I
H
1
ProMOS TECHNOLOGIES
V59C1G01(808/168)QC
Signal Pin Description
Pin
CK, CK
CKE
CS
RAS, CAS, WE
A0 - A13
Type
Input
Input
Input
Input
Input
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK.
Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the
Power Down mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be
executed by the SDRAM.
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled
at the rising clock edge for x8 and A0-A12 row address for x16 device.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled
at the rising clock edge.CAn depends on the SDRAM organization:
128M x 8 DDR CAn = CA9
64M x 16 DDR CAn = CA9
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the
bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control
which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless
of state of BA0 , BA1 and BA2.
BA0-BA2
DQx
DQS, (DQS)
LDQS, (LDQS)
UDQS, (UDQS)
RDQS, (RDQS)
Input
Input/
Output
Input/
Output
Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQ0-DQ7 for x8 device and DQ0-DQ15 for x16 device.
Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write
data. For x16 device, LDQS corresponds to the data on DQ0-DQ7; UDQS coresponds to the data on
DQ8-DQ15. For x8 device, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify
read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or
paired with optional complimentary signals DQS, LDQS, UDQS, and RDQS to provide differential pair
signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all
complementary data strobe signals.
DM is an input mask signal for write data. Input data is masked when DM is sampled high along with
that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading is designed to match that of DQ and DQS pins.
For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
For x16 device, LDM is DM for lower byte DQ0-DQ7 and UDM is DM for upper byte DQ8-DQ15.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
SSTL Reference Voltage for Inputs
Isolated power supply and ground for the DLL to provide improved noise immunity.
On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to
each DQ, DQS, DQS, RDQS, RDQS and DM for x8 device. For x16 configuration ODT is applied to
each DQ, UDQS/UDQS, LDQS/LDQS, UDM and LDM signal. ODT will be ignored if EMRS disable the
function.
DM,
LDM,UDM
Input
VDD, VSS
VDDQ, VSSQ
VREF
VDDL, VSSDL
ODT
Supply
Supply
Input
Supply
Input
V59C1G01(808/168)QC Rev.1.5 June 2012
5
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
