4Gb: x8, x16 Automotive DDR4 SDRAM
Features
Automotive DDR4 SDRAM
MT40A512M8, MT40A256M16
Features
•
•
•
•
•
V
DD
= V
DDQ
= 1.2V ±60mV
V
PP
= 2.5V –125mV/+250mV
On-die, internal, adjustable V
REFDQ
generation
1.2V pseudo open-drain I/O
Refresh maximum interval time at T
C
temperature
range:
– 64ms at –40°C to 85°C
– 32ms at 85°C to 95°C
– 16ms at 96°C to 105°C
– 8ms at 106°C to 125°C
16 internal banks ( x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register read and write capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
Hard post package repair (hPPR) and soft post
package repair (sPPR) modes
JEDEC JESD-79-4 compliant
Options
1
• Configuration
– 512 Meg x 8
– 256 Meg x 16
• BGA package (Pb-free) – x8
– 78-ball (9mm x 10.5mm) – Rev. B
– 78-ball (7.5mm x 11mm) – Rev. F
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) – Rev. B
– 96-ball (7.5mm x 13.5mm) – Rev. F
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
• Automotive grade
– AEC-Q100
– PPAP
• Operating temperature
– Industrial (–40°C
≤
T
C
≤
+95°C)
– Automotive (–40°C
≤
T
C
≤
+105°C)
– Ultra-high (–40°C
≤
T
C
≤
+125°C)
3
– Revision
Notes:
Marking
512M8
256M16
RH
SA, AG
GE
LY, AD
-062E
-075E
-083E
A
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IT
AT
UT
:B :F
1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on
http://www.micron.com
for
available offerings.
2. The ×4 device is not offered and the mode
is not supported by the x8 or x16 device
even though some ×4 mode descriptions ex-
ist in the datasheet.
3. The UT option use based on automotive us-
age model. Please contact Micron sales rep-
resentative if you have questions.
4. -062E is only available for die Rev. F.
Table 1: Key Timing Parameters
Speed Grade
-062E
1
-075E
1
-083E
Note:
Data Rate (MT/s)
3200
2666
2400
Target CL-nRCD-nRP
22-22-22
18-18-18
16-16-16
t
AA
(ns)
t
RCD
(ns)
t
RP
(ns)
13.75
13.5
13.32
13.75
13.5
13.32
13.75
13.5
13.32
1. Refer to the Speed Bin Tables for backward compatibility
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page size
1
Note:
512 Meg x 8
4
BG[1:0]
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
1KB
256 Meg x 16
2
BG0
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
2KB
1. Page size is per bank, calculated as follows:
Page size = 2
COLBITS
× ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
Figure 1: Order Part Number Example
Example Part Number: MT40A512M8RH-075E AAT:B
-
MT40A
Configuration
512 Meg x 8
256 Meg x 16
Configuration
Mark
512M8
256M16
Mark
RH
SA, AG
GE
LY, AD
Package
Speed
{
Revision
:B, :F
Package
78-ball 9.0mm x 10.5mm FBGA
78-ball 7.5mm x 11.0mm FBGA
96-ball 9.0mm x 14.0mm FBGA
96-ball 7.5mm x 13.5mm FBGA
Case Temperature
Commercial
Industrial
Automotive
Ultra-high
:
Revision
Mark
None
IT
AT
UT
Speed Grade
t
CK = 0.625ns, CL = 22
t
CK
t
CK
Mark
-062E
-075E
-083E
= 0.750ns, CL = 18
= 0.833ns, CL = 16
Product certification
Automotive
Mark
A
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
4Gb: x8, x16 Automotive DDR4 SDRAM
Features
Contents
Important Notes and Warnings .......................................................................................................................
General Notes and Description .......................................................................................................................
Description ................................................................................................................................................
Industrial Temperature ...............................................................................................................................
Automotive Temperature ............................................................................................................................
Ultra-high Temperature ..............................................................................................................................
General Notes ............................................................................................................................................
Definitions of the Device-Pin Signal Level ...................................................................................................
Definitions of the Bus Signal Level ...............................................................................................................
Functional Block Diagrams .............................................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Dimensions .......................................................................................................................................
State Diagram ................................................................................................................................................
Functional Description ...................................................................................................................................
RESET and Initialization Procedure .................................................................................................................
Power-Up and Initialization Sequence .........................................................................................................
RESET Initialization with Stable Power Sequence .........................................................................................
Uncontrolled Power-Down Sequence ..........................................................................................................
Programming Mode Registers .........................................................................................................................
Mode Register 0 ..............................................................................................................................................
Burst Length, Type, and Order .....................................................................................................................
CAS Latency ...............................................................................................................................................
Test Mode ..................................................................................................................................................
Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................
DLL RESET .................................................................................................................................................
Mode Register 1 ..............................................................................................................................................
DLL Enable/DLL Disable ............................................................................................................................
Output Driver Impedance Control ...............................................................................................................
ODT R
TT(NOM)
Values ..................................................................................................................................
Additive Latency .........................................................................................................................................
Rx CTLE Control .........................................................................................................................................
Write Leveling ............................................................................................................................................
Output Disable ...........................................................................................................................................
Termination Data Strobe .............................................................................................................................
Mode Register 2 ..............................................................................................................................................
CAS WRITE Latency ....................................................................................................................................
Low-Power Auto Self Refresh .......................................................................................................................
Dynamic ODT ............................................................................................................................................
Write Cyclic Redundancy Check Data Bus ....................................................................................................
Mode Register 3 ..............................................................................................................................................
Multipurpose Register ................................................................................................................................
WRITE Command Latency When CRC/DM is Enabled .................................................................................
Fine Granularity Refresh Mode ....................................................................................................................
Temperature Sensor Status .........................................................................................................................
Per-DRAM Addressability ...........................................................................................................................
Gear-Down Mode .......................................................................................................................................
Mode Register 4 ..............................................................................................................................................
Hard Post Package Repair Mode ..................................................................................................................
Soft Post Package Repair Mode ....................................................................................................................
18
18
18
19
19
19
19
20
20
21
22
24
27
33
35
36
36
39
40
41
44
45
46
47
47
47
48
49
50
50
50
50
51
51
51
52
54
54
54
54
55
56
57
57
57
57
57
58
59
59
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
4Gb: x8, x16 Automotive DDR4 SDRAM
Features
WRITE Preamble ........................................................................................................................................ 60
READ Preamble .......................................................................................................................................... 60
READ Preamble Training ............................................................................................................................ 60
Temperature-Controlled Refresh ................................................................................................................. 60
Command Address Latency ........................................................................................................................ 60
Internal V
REF
Monitor ................................................................................................................................. 60
Maximum Power Savings Mode ................................................................................................................... 61
MBIST-PPR ................................................................................................................................................ 61
Mode Register 5 .............................................................................................................................................. 62
Data Bus Inversion ..................................................................................................................................... 63
Data Mask .................................................................................................................................................. 64
CA Parity Persistent Error Mode .................................................................................................................. 64
ODT Input Buffer for Power-Down .............................................................................................................. 64
CA Parity Error Status ................................................................................................................................. 64
CRC Error Status ......................................................................................................................................... 64
CA Parity Latency Mode .............................................................................................................................. 64
Mode Register 6 .............................................................................................................................................. 65
Data Rate Programming .............................................................................................................................. 66
V
REFDQ
Calibration Enable .......................................................................................................................... 66
V
REFDQ
Calibration Range ........................................................................................................................... 66
V
REFDQ
Calibration Value ............................................................................................................................ 66
Truth Tables ................................................................................................................................................... 67
NOP Command .............................................................................................................................................. 70
DESELECT Command .................................................................................................................................... 70
DLL-Off Mode ................................................................................................................................................ 70
DLL-On/Off Switching Procedures .................................................................................................................. 72
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 72
DLL-Off to DLL-On Procedure .................................................................................................................... 74
Input Clock Frequency Change ....................................................................................................................... 75
Write Leveling ................................................................................................................................................ 76
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 77
Procedure Description ................................................................................................................................ 78
Write Leveling Mode Exit ............................................................................................................................ 79
Command Address Latency ............................................................................................................................ 81
Low-Power Auto Self Refresh Mode ................................................................................................................. 86
Manual Self Refresh Mode .......................................................................................................................... 86
Multipurpose Register .................................................................................................................................... 88
MPR Reads ................................................................................................................................................. 89
MPR Readout Format ................................................................................................................................. 91
MPR Readout Serial Format ........................................................................................................................ 91
MPR Readout Parallel Format ..................................................................................................................... 92
MPR Readout Staggered Format .................................................................................................................. 93
MPR READ Waveforms ............................................................................................................................... 94
MPR Writes ................................................................................................................................................ 96
MPR WRITE Waveforms .............................................................................................................................. 97
MPR REFRESH Waveforms ......................................................................................................................... 98
Gear-Down Mode .......................................................................................................................................... 101
Maximum Power-Saving Mode ....................................................................................................................... 104
Maximum Power-Saving Mode Entry .......................................................................................................... 104
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 105
CKE Transition During Maximum Power-Saving Mode ................................................................................ 105
Maximum Power-Saving Mode Exit ............................................................................................................ 105
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
4Gb: x8, x16 Automotive DDR4 SDRAM
Features
Command/Address Parity .............................................................................................................................. 107
Per-DRAM Addressability .............................................................................................................................. 115
V
REFDQ
Calibration ........................................................................................................................................ 118
V
REFDQ
Range and Levels ........................................................................................................................... 119
V
REFDQ
Step Size ........................................................................................................................................ 119
V
REFDQ
Increment and Decrement Timing .................................................................................................. 120
V
REFDQ
Target Settings ............................................................................................................................... 124
Connectivity Test Mode ................................................................................................................................. 126
Pin Mapping ............................................................................................................................................. 126
Minimum Terms Definition for Logic Equations ......................................................................................... 127
Logic Equations for a x4 Device .................................................................................................................. 127
Logic Equations for a x8 Device .................................................................................................................. 128
Logic Equations for a x16 Device ................................................................................................................ 128
CT Input Timing Requirements .................................................................................................................. 128
Excessive Row Activation ............................................................................................................................... 130
Post Package Repair ....................................................................................................................................... 131
Post Package Repair ................................................................................................................................... 131
Hard Post Package Repair .......................................................................................................................... 132
hPPR Row Repair - Entry ........................................................................................................................ 132
hPPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................. 132
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................. 134
sPPR Row Repair ....................................................................................................................................... 136
hPPR/sPPR/MBIST-PPR Support Identifier ................................................................................................. 139
ACTIVATE Command .................................................................................................................................... 139
PRECHARGE Command ................................................................................................................................ 140
REFRESH Command ..................................................................................................................................... 140
Temperature-Controlled Refresh Mode .......................................................................................................... 143
Normal Temperature Mode ........................................................................................................................ 143
Extended Temperature Mode ..................................................................................................................... 143
Fine Granularity Refresh Mode ....................................................................................................................... 146
Mode Register and Command Truth Table .................................................................................................. 146
t
REFI and
t
RFC Parameters ........................................................................................................................ 146
Changing Refresh Rate ............................................................................................................................... 149
Usage with TCR Mode ................................................................................................................................ 149
Self Refresh Entry and Exit ......................................................................................................................... 149
SELF REFRESH Operation .............................................................................................................................. 151
Self Refresh Abort ...................................................................................................................................... 153
Self Refresh Exit with NOP Command ......................................................................................................... 154
Power-Down Mode ........................................................................................................................................ 156
Power-Down Clarifications – Case 1 ........................................................................................................... 161
Power-Down Entry, Exit Timing with CAL ................................................................................................... 162
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 164
CRC Write Data Feature ................................................................................................................................. 166
CRC Write Data ......................................................................................................................................... 166
WRITE CRC DATA Operation ...................................................................................................................... 166
DBI_n and CRC Both Enabled .................................................................................................................... 167
DM_n and CRC Both Enabled .................................................................................................................... 167
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 167
CRC and Write Preamble Restrictions ......................................................................................................... 167
CRC Simultaneous Operation Restrictions .................................................................................................. 167
CRC Polynomial ........................................................................................................................................ 167
CRC Combinatorial Logic Equations .......................................................................................................... 168
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
京公网安备 11010802033920号
EEWORLD
