MT40A512M8SA-062EIT:F datasheet, PDF

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MT40A512M8SA-062EIT:F: DescriptionDDR DRAM, 512MX8, CMOS, PBGA78, FBGA-78; Categorystorage storage; File Size11MB，384 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT40A512M8SA-062EIT:F Overview

DDR DRAM, 512MX8, CMOS, PBGA78, FBGA-78

MT40A512M8SA-062EIT:F Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	8350852821
package instruction	TFBGA,
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78
JESD-609 code	e1
length	11 mm
memory density	4294967296 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	78
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature	-40 °C
organize	512MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.26 V
Minimum supply voltage (Vsup)	1.14 V
Nominal supply voltage (Vsup)	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	7.5 mm

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4Gb: x8, x16 Automotive DDR4 SDRAM

Features

Automotive DDR4 SDRAM

MT40A512M8, MT40A256M16

Features

•

= V

DDQ

= 1.2V ±60mV

= 2.5V –125mV/+250mV

On-die, internal, adjustable V

REFDQ

generation

1.2V pseudo open-drain I/O

Refresh maximum interval time at T

temperature

range:

– 64ms at –40°C to 85°C

– 32ms at 85°C to 95°C

– 16ms at 96°C to 105°C

– 8ms at 106°C to 125°C

16 internal banks ( x8): 4 groups of 4 banks each

8 internal banks (x16): 2 groups of 4 banks each

8n-bit prefetch architecture

Programmable data strobe preambles

Data strobe preamble training

Command/Address latency (CAL)

Multipurpose register read and write capability

Write leveling

Self refresh mode

Low-power auto self refresh (LPASR)

Temperature controlled refresh (TCR)

Fine granularity refresh

Self refresh abort

Maximum power saving

Output driver calibration

Nominal, park, and dynamic on-die termination

(ODT)

Data bus inversion (DBI) for data bus

Command/Address (CA) parity

Databus write cyclic redundancy check (CRC)

Per-DRAM addressability

Connectivity test

Hard post package repair (hPPR) and soft post

package repair (sPPR) modes

JEDEC JESD-79-4 compliant

Options

• Configuration

– 512 Meg x 8

– 256 Meg x 16

• BGA package (Pb-free) – x8

– 78-ball (9mm x 10.5mm) – Rev. B

– 78-ball (7.5mm x 11mm) – Rev. F

• FBGA package (Pb-free) – x16

– 96-ball (9mm x 14mm) – Rev. B

– 96-ball (7.5mm x 13.5mm) – Rev. F

• Timing – cycle time

– 0.625ns @ CL = 22 (DDR4-3200)

– 0.750ns @ CL = 18 (DDR4-2666)

– 0.833ns @ CL = 16 (DDR4-2400)

• Automotive grade

– AEC-Q100

– PPAP

• Operating temperature

– Industrial (–40°C

≤

+95°C)

– Automotive (–40°C

≤

+105°C)

– Ultra-high (–40°C

≤

+125°C)

– Revision

Notes:

Marking

512M8

256M16

SA, AG

LY, AD

-062E

-075E

-083E

•

:B :F

1. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on

http://www.micron.com

for

available offerings.

2. The ×4 device is not offered and the mode

is not supported by the x8 or x16 device

even though some ×4 mode descriptions ex-

ist in the datasheet.

3. The UT option use based on automotive us-

age model. Please contact Micron sales rep-

resentative if you have questions.

4. -062E is only available for die Rev. F.

Table 1: Key Timing Parameters

Speed Grade

-062E

-075E

-083E

Note:

Data Rate (MT/s)

3200

2666

2400

Target CL-nRCD-nRP

22-22-22

18-18-18

16-16-16

(ns)

RCD

(ns)

13.75

13.5

13.32

13.75

13.5

13.32

13.75

13.5

13.32

1. Refer to the Speed Bin Tables for backward compatibility

Micron Technology, Inc. reserves the right to change products or specifications without notice.

CCMTD-1725822587-10418

4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x8, x16 Automotive DDR4 SDRAM

Features

Contents

Important Notes and Warnings .......................................................................................................................

General Notes and Description .......................................................................................................................

Description ................................................................................................................................................

Industrial Temperature ...............................................................................................................................

Automotive Temperature ............................................................................................................................

Ultra-high Temperature ..............................................................................................................................

General Notes ............................................................................................................................................

Definitions of the Device-Pin Signal Level ...................................................................................................

Definitions of the Bus Signal Level ...............................................................................................................

Functional Block Diagrams .............................................................................................................................

Ball Assignments ............................................................................................................................................

Ball Descriptions ............................................................................................................................................

Package Dimensions .......................................................................................................................................

State Diagram ................................................................................................................................................

Functional Description ...................................................................................................................................

RESET and Initialization Procedure .................................................................................................................

Power-Up and Initialization Sequence .........................................................................................................

RESET Initialization with Stable Power Sequence .........................................................................................

Uncontrolled Power-Down Sequence ..........................................................................................................

Programming Mode Registers .........................................................................................................................

Mode Register 0 ..............................................................................................................................................

Burst Length, Type, and Order .....................................................................................................................

CAS Latency ...............................................................................................................................................

Test Mode ..................................................................................................................................................

Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................

DLL RESET .................................................................................................................................................

Mode Register 1 ..............................................................................................................................................

DLL Enable/DLL Disable ............................................................................................................................

Output Driver Impedance Control ...............................................................................................................

ODT R

TT(NOM)

Values ..................................................................................................................................

Additive Latency .........................................................................................................................................

Rx CTLE Control .........................................................................................................................................

Write Leveling ............................................................................................................................................

Output Disable ...........................................................................................................................................

Termination Data Strobe .............................................................................................................................

Mode Register 2 ..............................................................................................................................................

CAS WRITE Latency ....................................................................................................................................

Low-Power Auto Self Refresh .......................................................................................................................

Dynamic ODT ............................................................................................................................................

Write Cyclic Redundancy Check Data Bus ....................................................................................................

Mode Register 3 ..............................................................................................................................................

Multipurpose Register ................................................................................................................................

WRITE Command Latency When CRC/DM is Enabled .................................................................................

Fine Granularity Refresh Mode ....................................................................................................................

Temperature Sensor Status .........................................................................................................................

Per-DRAM Addressability ...........................................................................................................................

Gear-Down Mode .......................................................................................................................................

Mode Register 4 ..............................................................................................................................................

Hard Post Package Repair Mode ..................................................................................................................

Soft Post Package Repair Mode ....................................................................................................................

CCMTD-1725822587-10418

4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x8, x16 Automotive DDR4 SDRAM

Features

WRITE Preamble ........................................................................................................................................ 60

READ Preamble .......................................................................................................................................... 60

READ Preamble Training ............................................................................................................................ 60

Temperature-Controlled Refresh ................................................................................................................. 60

Command Address Latency ........................................................................................................................ 60

Internal V

REF

Monitor ................................................................................................................................. 60

Maximum Power Savings Mode ................................................................................................................... 61

MBIST-PPR ................................................................................................................................................ 61

Mode Register 5 .............................................................................................................................................. 62

Data Bus Inversion ..................................................................................................................................... 63

Data Mask .................................................................................................................................................. 64

CA Parity Persistent Error Mode .................................................................................................................. 64

ODT Input Buffer for Power-Down .............................................................................................................. 64

CA Parity Error Status ................................................................................................................................. 64

CRC Error Status ......................................................................................................................................... 64

CA Parity Latency Mode .............................................................................................................................. 64

Mode Register 6 .............................................................................................................................................. 65

Data Rate Programming .............................................................................................................................. 66

REFDQ

Calibration Enable .......................................................................................................................... 66

REFDQ

Calibration Range ........................................................................................................................... 66

REFDQ

Calibration Value ............................................................................................................................ 66

Truth Tables ................................................................................................................................................... 67

NOP Command .............................................................................................................................................. 70

DESELECT Command .................................................................................................................................... 70

DLL-Off Mode ................................................................................................................................................ 70

DLL-On/Off Switching Procedures .................................................................................................................. 72

DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 72

DLL-Off to DLL-On Procedure .................................................................................................................... 74

Input Clock Frequency Change ....................................................................................................................... 75

Write Leveling ................................................................................................................................................ 76

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 77

Procedure Description ................................................................................................................................ 78

Write Leveling Mode Exit ............................................................................................................................ 79

Command Address Latency ............................................................................................................................ 81

Low-Power Auto Self Refresh Mode ................................................................................................................. 86

Manual Self Refresh Mode .......................................................................................................................... 86

Multipurpose Register .................................................................................................................................... 88

MPR Reads ................................................................................................................................................. 89

MPR Readout Format ................................................................................................................................. 91

MPR Readout Serial Format ........................................................................................................................ 91

MPR Readout Parallel Format ..................................................................................................................... 92

MPR Readout Staggered Format .................................................................................................................. 93

MPR READ Waveforms ............................................................................................................................... 94

MPR Writes ................................................................................................................................................ 96

MPR WRITE Waveforms .............................................................................................................................. 97

MPR REFRESH Waveforms ......................................................................................................................... 98

Gear-Down Mode .......................................................................................................................................... 101

Maximum Power-Saving Mode ....................................................................................................................... 104

Maximum Power-Saving Mode Entry .......................................................................................................... 104

Maximum Power-Saving Mode Entry in PDA .............................................................................................. 105

CKE Transition During Maximum Power-Saving Mode ................................................................................ 105

Maximum Power-Saving Mode Exit ............................................................................................................ 105

CCMTD-1725822587-10418

4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x8, x16 Automotive DDR4 SDRAM

Features

Command/Address Parity .............................................................................................................................. 107

Per-DRAM Addressability .............................................................................................................................. 115

REFDQ

Calibration ........................................................................................................................................ 118

REFDQ

Range and Levels ........................................................................................................................... 119

REFDQ

Step Size ........................................................................................................................................ 119

REFDQ

Increment and Decrement Timing .................................................................................................. 120

REFDQ

Target Settings ............................................................................................................................... 124

Connectivity Test Mode ................................................................................................................................. 126

Pin Mapping ............................................................................................................................................. 126

Minimum Terms Definition for Logic Equations ......................................................................................... 127

Logic Equations for a x4 Device .................................................................................................................. 127

Logic Equations for a x8 Device .................................................................................................................. 128

Logic Equations for a x16 Device ................................................................................................................ 128

CT Input Timing Requirements .................................................................................................................. 128

Excessive Row Activation ............................................................................................................................... 130

Post Package Repair ....................................................................................................................................... 131

Post Package Repair ................................................................................................................................... 131

Hard Post Package Repair .......................................................................................................................... 132

hPPR Row Repair - Entry ........................................................................................................................ 132

hPPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................. 132

hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................. 134

sPPR Row Repair ....................................................................................................................................... 136

hPPR/sPPR/MBIST-PPR Support Identifier ................................................................................................. 139

ACTIVATE Command .................................................................................................................................... 139

PRECHARGE Command ................................................................................................................................ 140

REFRESH Command ..................................................................................................................................... 140

Temperature-Controlled Refresh Mode .......................................................................................................... 143

Normal Temperature Mode ........................................................................................................................ 143

Extended Temperature Mode ..................................................................................................................... 143

Fine Granularity Refresh Mode ....................................................................................................................... 146

Mode Register and Command Truth Table .................................................................................................. 146

REFI and

RFC Parameters ........................................................................................................................ 146

Changing Refresh Rate ............................................................................................................................... 149

Usage with TCR Mode ................................................................................................................................ 149

Self Refresh Entry and Exit ......................................................................................................................... 149

SELF REFRESH Operation .............................................................................................................................. 151

Self Refresh Abort ...................................................................................................................................... 153

Self Refresh Exit with NOP Command ......................................................................................................... 154

Power-Down Mode ........................................................................................................................................ 156

Power-Down Clarifications – Case 1 ........................................................................................................... 161

Power-Down Entry, Exit Timing with CAL ................................................................................................... 162

ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 164

CRC Write Data Feature ................................................................................................................................. 166

CRC Write Data ......................................................................................................................................... 166

WRITE CRC DATA Operation ...................................................................................................................... 166

DBI_n and CRC Both Enabled .................................................................................................................... 167

DM_n and CRC Both Enabled .................................................................................................................... 167

DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 167

CRC and Write Preamble Restrictions ......................................................................................................... 167

CRC Simultaneous Operation Restrictions .................................................................................................. 167

CRC Polynomial ........................................................................................................................................ 167

CRC Combinatorial Logic Equations .......................................................................................................... 168

CCMTD-1725822587-10418

4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT40A512M8SA-062EIT:F Related Products

	MT40A512M8SA-062EIT:F	MT40A256M16LY-062EAIT:F	MT40A512M8SA-062EAUT:F	MT40A256M16LY-062EAUT:F
Description	DDR DRAM, 512MX8, CMOS, PBGA78, FBGA-78	MT40A256M16LY-062EAIT:F,	MT40A512M8SA-062EAUT:F,	MT40A256M16LY-062EAUT:F,
Objectid	8350852821	7322189070	7322189116	7322189072
package instruction	TFBGA,	TFBGA, BGA96,9X16,32	TFBGA, BGA78,9X13,32	TFBGA, BGA96,9X16,32
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
JESD-30 code	R-PBGA-B78	R-PBGA-B96	R-PBGA-B78	R-PBGA-B96
length	11 mm	13.5 mm	11 mm	13.5 mm
memory density	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bit
Memory IC Type	DDR DRAM	DDR4 DRAM	DDR4 DRAM	DDR4 DRAM
memory width	8	16	8	16
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	78	96	78	96
word count	536870912 words	268435456 words	536870912 words	268435456 words
character code	512000000	256000000	512000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	95 °C	95 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	512MX8	256MX16	512MX8	256MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.26 V	1.26 V	1.26 V	1.26 V
Minimum supply voltage (Vsup)	1.14 V	1.14 V	1.14 V	1.14 V
Nominal supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	AUTOMOTIVE	AUTOMOTIVE
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-
I/O type	-	COMMON	COMMON	COMMON
interleaved burst length	-	8	8	8
Output characteristics	-	3-STATE	3-STATE	OPEN-DRAIN
Encapsulate equivalent code	-	BGA96,9X16,32	BGA78,9X13,32	BGA96,9X16,32
Filter level	-	AEC-Q100	AEC-Q100	AEC-Q100
Continuous burst length	-	8	8	8
Maximum standby current	-	0.046 A	0.049 A	0.05 A
Minimum standby current	-	1.14 V	1.14 V	1.14 V
Maximum slew rate	-	0.056 mA	0.053 mA	0.06 mA

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