Input reflected-ripple current is measured with an inductor Lin and Capacitor Cin to simulate source impedance.
Oscilloscope
Lin
Cin
Lin(4.7µH)
Current
Probe
DC DC
Load
Cin(220µF, ESR < 1.0Ω at 100 KHz)
DESIGN CONSIDERATIONS
1) Requirement on output load
To ensure this module can operate efficiently and reliably, during operation, the minimum output load could not be less than 5% of the full load.
otherwise ripple maybe increase dramatically. If the actual output power is very small, please connect a resistor with proper resistance at the output end
in parallel to increase the load, suppose to use the resistance of 5% rated power, or use our company’s products with a lower rated output power.
2) Recommended circuit
All the PWB_ZP-3WR2 Series have been tested according to the following recommended testing circuit before leaving factory (see Figure 5).
If you want to further decrease the input/output ripple, you can increase a capacitance properly or choose capacitors with low ESR. However, the
capacitance of the output filter capacitor must be proper. If the capacitance is too big, a startup problem might arise. The safe and reliable operation is
ensured, the greatest capacitance of its filter capacitor must be less than the Max. Capacitive Load.
General: Cin: 10μF~47μF
Cout: 10μF/100mA
Vin
Cin
+Vo
DC
DC
(Figure 5)
Cou t
GND
0V
3) Input current
When it is used in unregulated power supply, be sure that the fluctuating range of the power supply and the rippled voltage do not exceed the
module standard. Input current of power supply should afford the flash startup current of this kind of DC/DC module (Figure 6).
General: Vin:24V Ip =640mA
Vin:48V Ip =320mA
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FPGA/CPLD
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