EEWORLDEEWORLDEEWORLD

Part Number

Search

54121-408-18-1700

Description
Board Connector, 18 Contact(s), 1 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle,
CategoryThe connector    The connector   
File Size101KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

54121-408-18-1700 Overview

Board Connector, 18 Contact(s), 1 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle,

54121-408-18-1700 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid305724113
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL6.83
body width0.094 inch
subject depth0.669 inch
body length1.8 inch
Body/casing typeRECEPTACLE
Connector typeBOARD CONNECTOR
Contact to complete cooperationSN ON NI
Contact completed and terminatedTin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
contact modeRECTANGULAR
Contact styleSQ PIN-SKT
Insulation resistance5000000000 Ω
Insulator colorBLACK
insulator materialPOLYETHYLENE
JESD-609 codee0
Manufacturer's serial number54121
Plug contact pitch0.1 inch
Installation option 1LOCKING
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number1
Number of rows loaded1
Maximum operating temperature125 °C
Minimum operating temperature-65 °C
PCB contact patternRECTANGULAR
Plating thickness79u inch
Rated current (signal)3 A
GuidelineUL, CSA
reliabilityCOMMERCIAL
Terminal length0.095 inch
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts18
PDM: Rev:G
STATUS:
Released
Printed: Mar 10, 2011
.
Analog Electronics Course Selection Test
Watch the courses on the course list...
amperhong TI Technology Forum
About SPI mode setting
For SPI communication, there are only four pins: MOSI, MISO, CS, and CLK. SPI has four modes. So how do you set the various modes when using SPI? There are no clock polarity and phase pins?...
shijizai 51mcu
[FPGA Design Tips] Several concepts about FPGA clocks: delay, intermediate state and speed
InWhen the delay of data transfer between registers exceeds one clock cycle, the downstream register cannot sample the upstream data given in the current clock cycle in the next clock cycle, and an er...
eeleader FPGA/CPLD
Is there anyone who has ported the FLASH player to WINCE?
As the title says, if anyone has this question, please contact QQ: 414858335...
eddy326 Embedded System
Summary of works participating in the "Willful DIY" activity
[font=微软雅黑][size=3]This post is a collection of works participating in the "任性DIY" event. If you haven't participated in the event yet, hurry up and join us! [/size][/font][font=微软雅黑][size=3] [/size][...
eric_wang DIY/Open Source Hardware
[Sipeed LicheeRV 86 Panel Review] 14. lvgl displays images and local time
[i=s]This post was last edited by sonicfirr on 2022-4-25 21:03[/i]This article records the process of using the lvgl framework to display pictures, and also obtains the local time of the system and di...
sonicfirr Domestic Chip Exchange

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1070  1810  1231  1257  2015  22  37  25  26  41 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号