HT93LC66
CMOS 4K 3-Wire Serial EEPROM
Features
·
Operating voltage: 2.2V~5.5V
·
Low power consumption
-
Operating: 5mA max.
-
Standby: 10mA max.
·
User selectable internal organization
-
4K(HT93LC66): 512´8 or 256´16
·
3-wire Serial Interface
·
Write cycle time: 5ms max.
·
Automatic erase-before-write operation
·
Word/chip erase and write operation
·
Write operation with built-in timer
·
Software controlled write protection
·
40-year data retention
·
10
6
rewrite cycles per word
·
Commercial temperature range (0°C to +70°C)
·
8-pin DIP/SOP/TSSOP package
General Description
The HT93LC66 is a 4K-bit low voltage nonvolatile, serial
electrically erasable programmable read only memory de-
vice using the CMOS floating gate process. Its 4096 bits of
memory are organized into 256 words of 16 bits each
when the ORG pin is connected to VCC or organized into
512 words of 8 bits each when it is tied to VSS. The device
is optimized for use in many industrial and commercial ap-
plications where low power and low voltage operation are
essential. By popular microcontroller, the versatile serial
interface including chip select (CS), serial clock (SK), data
input (DI) and data output (DO) can be easily controlled.
Block Diagram
C o n tro l
L o g ic
a n d
C lo c k
G e n e ra to r
A d d re s s
R e g is te r
V C C
A d d re s s
D e c o d e r
V S S
C S
S K
O R G
D I
D a ta
R e g is te r
M e m o r y C e ll
A rra y
4 K : (5 1 2
´
8 o r 2 5 6
´
1 6 )
O u tp u t
B u ffe r
D O
Pin Assignment
C S
1
8
2
7
3
6
4
5
S K
D I
D O
V C C
N C
O R G
V S S
N C
1
V C C
2
C S
S K
4
3
8
7
6
5
H T 9 3 L C 6 6
8 S O P -B
O R G
V S S
D O
D I
H T 9 3 L C 6 6
8 D IP -A /S O P -A /T S S O P -A
Rev. 1.70
1
July 10, 2009
HT93LC66
Functional Description
The HT93LC66 is accessed via a three-wire serial com-
munication interface. The device is arranged into 256
words by 16 bits or 512 words by 8 bits depending whether
the ORG pin is connected to VCC or VSS. The HT93LC66
contains seven instructions: READ, ERASE, WRITE,
EWEN, EWDS, ERAL and WRAL. When the user
selectable internal organization is arranged into
256´16 (512´8), these instructions are all made up of
11(12) bits data: 1 start bit, 2 op code bits and 8(9) address
bits.
By using the control signal CS, SK and data input signal
DI, these instructions can be given to the HT93LC66.
These serial instruction data presented at the DI input
will be written into the device at the rising edge of SK.
During the READ cycle, DO pin acts as the data output
and during the WRITE or ERASE cycle, DO pin indi-
cates the BUSY/READY status. When the DO pin is ac-
tive for read data or as a BUSY/READY indicator the CS
pin must be high; otherwise DO pin will be in a high-im-
pedance state. For successful instructions, CS must be
low once after the instruction is sent. After power on, the
device is by default in the EWDS state. And, an EWEN
instruction must be performed before any ERASE or
WRITE instruction can be executed. The following are
the functional descriptions and timing diagrams of all
seven instructions.
READ
The READ instruction will stream out data at a specified
address on the DO pin. The data on DO pin changes
during the low-to-high edge of SK signal. The 8 bits or
16 bits data stream is preceded by a logical
²0²
dummy
bit. Irrespective of the condition of the EWEN or EWDS
instruction, the READ command is always valid and in-
dependent of these two instructions. After the data word
has been read the internal address will be automatically
incremented by 1 allowing the next consecutive data
word to be read out without entering further address
data. The address will wrap around with CS High until
CS returns to LOW.
EWEN/EWDS
The EWEN/EWDS instruction will enable or disable the
programming capabilities. At both the power on and
power off state the device automatically entered the dis-
able mode. Before a WRITE, ERASE, WRAL or ERAL in-
struction is given, the programming enable instruction
EWEN must be issued, otherwise the ERASE/WRITE in-
struction is invalid. After the EWEN instruction is issued,
the programming enable condition remains until power is
turned off or a EWDS instruction is given. No data can be
written into the device in the programming disabled state.
By so doing, the internal memory data can be protected.
ERAL
The ERAL instruction erases the entire 256´16 or 512´8
memory cells to logical
²1²
state in the programming en-
able mode. After the erase-all instruction set has been
issued, the data erase feature is activated by the falling
edge of CS. Since the internal auto-timing generator
provides all timing signal for the erase-all operation, so
the SK clock is not required. During the internal erase-all
operation, we can verify the busy/ready status if CS is
high. The DO pin will remain low but when the operation
is over, the DO pin will return to high and further instruc-
tion can be executed.
WRAL
The WRAL instruction writes data into the entire 256´16
or 512´8 memory cells in the programming enable
mode. After the write-all instruction set has been issued,
the data writing is activated by the falling edge of CS.
Since the internal auto-timing generator provides all tim-
ing signals for the write-all operation, so the SK clock is
not required. During the internal write-all operation, we
can verify the busy/ready status if CS is high. The DO
pin will remain low but when the operation is over the
DO pin will return to high and further instruction can be
executed.
ERASE
The ERASE instruction erases data at the specified ad-
dresses in the programming enable mode. After the
ERASE op-code and the specified address have been
issued, the data erase is activated by the falling edge of
CS. Since the internal auto-timing generator provides all
timing signals for the internal erase, so the SK clock is
not required. During the internal erase, we can verify the
busy/ready status if CS is high. The DO pin will remain
low but when the operation is over, the DO pin will return
to high and further instructions can be executed.
WRITE
The WRITE instruction writes data into the device at the
specified addresses in the programming enable mode.
After the WRITE op-code and the specified address and
data have been issued, the data writing is activated by
the falling edge of CS. Since the internal auto-timing
generator provides all timing signal for the internal writ-
ing, so the SK clock is not required. The auto-timing
write cycle includes an automatic erase-before-write ca-
pability. So, it is not necessary to erase data before the
WRITE instruction. During the internal writing, we can
verify the busy/ready status if CS is high. The DO pin will
remain low but when the operation is over, the DO pin
will return to high and further instructions can be exe-
cuted.
Rev. 1.70
4
July 10, 2009
Renesas Electronics MCUs
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