Vectron’s VC-826 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off a 2.5 or 3.3 volt power supply
in a hermetically sealed 3.2 x 2.5mm ceramic package.
Features
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Ultra Low Jitter Performance, 3rd OT or Fundamental Crystal Design
20MHz -170MHz Output Frequencies
Low Power
Excellent Power Supply Rejection Ratio
Enable/Disable
3.3 or 2.5V operation
-10/70°C or -40/85°C Operation
Hermetically Sealed 3.2x2.5mm Ceramic Package
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Applications
Ethernet, GbE, Synchronous Ethernet
Fiber Channel
Enterprise Servers
Telecom
Clock source for A/D’s, D/A’s
Driving FPGA’s
Test and Measurement
PON
Medical
COTS
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
Complementary
Output
Output
V
DD
Voltage Regulator
Crystal
Oscillator
E/D or NC E/D or NC
Page1
GND
Performance Specifications
Table 1. Electrical Performance, LVPECL Option
Parameter
Voltage
1
Current
2
, 3.3V
2.5V
Nominal Frequency
Stability
3
(Ordering Option)
Outputs
Output Logic Levels
2
Output Logic High
Output Logic Low
Output Rise and Fall Time
2
Load
Duty Cycle
4
Phase Noise, 3.3V, 100MHz
5
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
20MHz
40MHz
Jitter
5
, 100MHz
12kHz -20MHz
Outputs Enabled
6
Outputs Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
t
SU
T
OP
-10/70 or -40/85
3.2 x 2.5 x 1.05
фJ
Enable/Disable
V
IH
V
IL
t
D
0.7*V
DD
0.3*V
DD
200
±200
10
V
V
ns
uA
ms
°C
mm
45
-70
-100
-126
-140
-146
-149
-157
-157
170
200
V
OH
V
OL
t
R
/t
F
50 ohms into V
DD
-1.3V
55
%
dBc/Hz
V
DD
-1.025
V
DD
-1.810
V
DD
-0.880
V
DD
-1.620
500
V
V
ps
Symbol
V
DD
I
DD
Min
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
45
42
Units
V
V
mA
Frequency
f
N
20
±25, ±50 or ±100
170
MHz
ppm
fs
1. The VC-826 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor.
2. Figure 1 defines the test circuit and Figure 2 defines these parameters.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Duty Cycle is defined as the On/Time Period.
5. Measured using an Agilent E5052 Signal Source Analyzer at 25 °C.
6. Outputs will be Enabled if Enable/Disable is left open.
t
R
V
AMP
*0.8
Cross Point
V
AMP
*0.2
On Time
Period
Figure 1.
Page2
t
F
V
AMP
Figure 2.
Performance Specifications
Table 2. Electrical Performance, LVDS Option
Parameter
Voltage
1
Current
2
, 3.3V
2.5V
Nominal Frequency
Stability
3
(Ordering Option)
Outputs
Output Logic Levels
2
Output Logic High
Output Logic Low
Output Amplitude
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current, Outputs Disabled
Output Rise and Fall Time
3
Load
Duty Cycle
4
Phase Noise, 3.3V, 100MHz
5
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
20MHz
40MHz
Jitter
5
, 100MHz
12kHz - 20MHz
Outputs Enabled
6
Outputs Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
фJ
Enable/Disable
V
IH
V
IL
t
D
I
E/D
t
SU
T
OP
-10/70 or -40/85
3.2 x 2.5 x 1.05
0.7*V
DD
0.3*V
DD
200
±200
10
V
V
ns
uA
ms
°C
mm
45
-73
-101
-128
-140
-147
-150
-156
-156
170
200
t
R
/t
F
100 ohms differential
55
%
dBc/Hz
1.125
1.25
V
OH
V
OL
1.43
1.10
350
1.6
454
50
1.375
50
10
500
V
V
mV
mV
V
mV
uA
ps
Symbol
Supply
V
DD
I
DD
Min
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
17
14
Units
V
V
mA
Frequency
f
N
20
±25, ±50 or ±100
170
MHz
ppm
0.9
247
fs
1.
The VC-826 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor.
2. Figure 2 defines these parameters and Figure 3 defines the test circuit.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Duty Cycle is defined as the On/Time Period.
5. Measured using an Agilent E5052 Signal Source Analyzer at 25 °C
6. Outputs will be Enabled if Enable/Disable is left open.
Figure 3.
Page3
Package Outline Drawing and Pad Layout
Marking Information
XXXMXX - Frequency (Example: 100M00)
YY - Year of Manufacture
WW - Week of the Year
C - Manufacturing Location
- Pin 1 Indicator
XXXMXX
YYWW C
Dimensions in mm
Table 3. Pinout
Pin #
1
2
3
4
5
6
Symbol
E/D or NC
E/D or NC
GND
f
O
Cf
O
V
DD
Function
Enable/Disable or No Connection
Enable/Disable or No Connection
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
Table 4. Enable Disable Function
E/D Pin
High
Open
Low
Output
Clock Output
Clock Output
High Impedance
Phase Noise (LV-PECL Output)
Page4
LVPECL Application Diagrams
Figure 4. Single Resistor Termination Scheme
Resistor values are typically 140 ohms for 3.3V operation and
84 ohms for 2.5V operation.
Figure 5. Pull-Up Pull Down Termination
Resistor values shown are typical for 3.3 V opertaion. For 2.5V operation, the
resistor to ground is 62 ohms and the resistor to supply is 250 ohms
The VC-826 incorporates a standard PECL output scheme, which are un-terminated FET drains. There are numerous application notes on terminating and
interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, or for best 50 ohm matching a pull-up/pull-down
scheme as shown in Figure 5 should be used. AC coupling capacitors are optional, depending on the application and the input logic requirements of the
next stage.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
LVDS Application Diagrams
Figure 6. LVDS to LVDS Connection, Internal 100ohm Resistor
Some LVDS structures have an internal 100 ohm resistor on the in-
put and do not need additional components. AC blocking capacitors
can be used if the DC levels are incompatible.
Figure 7. LVDS to LVDS Connection
Some input structures may not have an internal 100 ohm resis-
tor on the input and will need an external 100ohm resistor for
impedance matching. Also, the input may have an internal DC
bias which may not be compatible with LVDS levels, AC block-
ing capacitors can be used.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
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