Product Specification
IXD5118
Voltage Detector with Sense Input and Adjustable Delay
FEATURES
Accuracy ± 2% at V
DF
≥ 1.5 V or ±0.03 V
Low Power Consumption
0.4 μA (Detect at V
IN
= 1.0 V)
0.6 µA (Release at V
IN
= 1.0 V)
Detect Voltage Range 0.8 V – 5.0 V in 0.1 V
increments
Operating Voltage Range 1.0 V – 6.0 V
0
Detect Voltage Temperature Drift ±100 ppm/ C
Output Configuration CMOS (Version C) or N-
channel Open Drain (N Version)
Adjustable Release Time
0
Operating Ambient Temperature - 40 + 85 C
Packages : USP-4 and SOT-25
EU RoHS Compliant, Pb Free
DESCRIPTION
The IXD5118 are highly precise, low power
consumption,
CMOS
voltage
detectors,
manufactured using laser trimming technology.
Separated sense input allows the IXD5118 to monitor
other voltage source and maintain the state of
detection even if sense voltage falls to zero.
The external capacitor connected to the C
D
pin allows
adjusting of release delay time in a wide range.
With low power consumption and high accuracy, this
series is suitable for precision mobile equipment.
The IXD5118 in ultra small packages are ideally
suited for high-density PC boards.
The IXD5118 is available in both CMOS and N-
channel open drain output configurations.
This detector is available in USP-4 and SOT-25
packages.
APPLICATIONS
Microprocessor reset circuitry
Memory battery back-up circuits
Power-on reset circuits
Power failure detection
System battery life and charge voltage monitors
TYPICAL APPLICATION CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTIC
Output Voltage vs. Sense Voltage
IXD5118C25AGR
Ta = 25 C
0
Pull-up
Resistor R
PL
used with N-channel output configuaration only
PS037301-0615
PRELIMINARY
1
Product Specification
IXD5118
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input Voltage
Output Current
CMOS Output
Output
Voltage
N-channel Open Drain
Sense Pin Voltage
C
D
Pin Voltage
C
D
Pin Current
USP-4
Power Dissipation
SOT-25
Operating Temperature Range
Storage Temperature Range
All voltages are in respect to V
SS
SYMBOL
V
IN
I
OUT
V
OUT
V
SEN
V
CD
I
CD
P
D
T
OPR
T
STG
RATINGS
– 0.3 ~ +7.0
10
– 0.3 ~ V
IN
+ 0.3
– 0.3 ~ +7.0
– 0.3 ~ +7.0
– 0.3 ~ V
IN
+ 0.3
5.0
120
250
– 40 ~ + 85
– 55 ~ +125
UNITS
V
mA
V
V
V
mA
mW
0
0
C
C
ELECTRICAL OPERATING CHARACTERISTICS
Ta = 25
0
C
PARAMETER
Operating Voltage
Detect Voltage
Hysteresis Width
Detect Voltage Line
Regulation
Supply Current1
3)
Supply Current2
3)
I
SS1
I
SS2
SYMBOL
V
IN
V
DF
V
HYS
CONDITIONS
V
DF(T)
= 0.8 – 5.0 V
1)
V
IN
= 1.0 – 6.0 V
IXD5118xxxA
V
IN
= 1.0 – 6.0 V
IXD5118xxxB
V
IN
= 1.0 – 6.0 V
V
SEN
= V
DF
x 0.9
V
SEN
= V
DF
x 1.1
V
IN
= 1.0 V,
V
IN
= 6.0 V
V
IN
= 1.0 V,
V
IN
= 6.0 V
V
IN
= 1.0 V
V
IN
= 2.0 V
V
IN
= 3.0 V
V
IN
= 4.0 V
V
IN
= 5.0 V
V
IN
= 6.0 V
V
IN
= 1.0 V
V
IN
= 6.0 V
V
SEN
= V
OUT
= 0 V,
V
IN
= 6.0 V, C
D
- open
V
SEN
= V
OUT
= 6.0 V,
V
IN
= 6.0 V, C
D
- open
MIN.
1.0
E-1
E-2
2)
E-3
±0.1
0.4
0.4
0.8
0.9
0.7
1.6
2.0
2.3
2.4
2.5
-0.30
-1.0
-0.20
µA
0.20
± 100
E-4
2.0
200
0.5
3.0
0.3
30
30
0.40
ppm/
0
C
MΩ
MΩ
µA
V
V
µs
µs
1.0
1.0
1.6
1.8
2)
TYP.
MAX.
6.0
UNIT
V
V
V
%/V
µA
µA
CIRCUIT
I
OUT1
Output Current
V
SEN
= 0 V, V
DS
= 0.5 V
N-channel MOSFET
0.1
0.8
1.2
1.6
1.8
1.9
mA
I
OUT24)
Leakage Current
Detect Voltage
Temperature
Characteristics
Sense Pin Resistance
Delay Pin Resistance
C
D
Pin Sink Current
C
D
Pin Threshold
Voltage
Undefined Operation
Detect Delay Time
8)
Release Delay Time
9)
NOTE:
1)
2)
3)
4)
5)
6)
I
LEAK
V
SEN
= 6.0 V, V
DS
= 0.5 V
P-channel MOSFET
IXD5118Cxxx
(P-channel)
IXD5118Nxxx
(N-channel)
-0.08
-0.70
mA
- 40
0
C ≤ T
OPR
≤ 85
0
C
R
SEN5)
R
DEL6)
I
CD
V
TCD
V
UND4, 7)
t
DF0
t
DR0
V
SEN
= 6.0 V, V
IN
= 0 V
V
SEN
= 6.0 V, V
IN
= 5.0 V, V
CD
= 0 V
V
IN
= 1.0 V, V
CD
= 0.5 V
V
SEN
= 6.0 V, V
IN
= 1.0 V
V
SEN
= 6.0 V, V
IN
= 6.0 V
V
SEN
= V
IN
= 0
1.0 V
V
IN
= 6.0 V, V
SEN
= 6.0
0 V, C
D
- open
V
IN
= 6.0 V, V
SEN
= 0
6.0 V, C
D
- open
7)
8)
9)
1.6
0.4
2.9
2.4
0.6
3.1
0.4
230
200
V
DF(T
) is a nominal detect voltage
Please refer to the table named Voltage Chart
Current to the sense resistor is not included
IXD5118C version only
It is calculated from the voltage value and the current value
of the V
SEN
It is calculated from the voltage value of the V
IN
and the
current value of the C
D
pin
Maximum V
OUT
voltage at V
IN
rising from 0V to 1.0V with the
V
IN
pin connected to the V
SEN
pin
Delay time from the moment, when V
SEN
= V
DF
to the
moment, when V
OUT
= 0.6 V, at V
SEN
falling
Delay time from the moment, when V
SEN
= V
DF
+ V
HYS
to the
moment, when V
OUT
= 5.4 V at V
SEN
rising
PS037301-0615
PRELIMINARY
2
Product Specification
IXD5118
ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED)
Voltage Chart
SYMBOL
NOMINAL
VOLTAGE
V
DF(T)
(V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
NOTE:
1)
When V
DF(T)
≤ 1.4 V, the detection accuracy is ±30mV; when V
DF(T)
≥ 1.5 V, the detection accuracy is ±2%.
E-1
1)
DETECT VOLTAGE (V)
V
DF
MIN.
0.770
0.870
0.970
1.070
1.170
1.270
1.370
1.470
1.568
1.666
1.764
1.862
1.960
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
3.528
3.626
3.724
3.822
3.920
4.018
4.116
4.214
4.312
4.410
4.508
4.606
4.704
4.802
4.900
MAX.
0.830
0.930
1.030
1.130
1.230
1.330
1.430
1.530
1.632
1.734
1.836
1.938
2.040
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
3.672
3.774
3.876
3.978
4.080
4.182
4.284
4.386
4.488
4.590
4.692
4.794
4.896
4.998
5.100
MIN.
0.015
0.017
0.019
0.021
0.023
0.025
0.027
0.029
0.031
0.033
0.035
0.037
0.039
0.041
0.043
0.045
0.047
0.049
0.051
0.053
0.055
0.057
0.059
0.061
0.063
0.065
0.067
0.069
0.071
0.073
0.074
0.076
0.078
0.080
0.082
0.084
0.086
0.088
0.090
0.092
0.094
0.096
0.098
E-2
HYSTERESIS RANGE (V)
V
HYS
MAX.
0.066
0.074
0.082
0.090
0.098
0.106
0.114
0.122
0.131
0.085
0.147
0.155
0.163
0.171
0.180
0.188
0.196
0.204
0.212
0.220
0.228
0.237
0.245
0.253
0.261
0.269
0.277
0.286
0.294
0.302
0.310
0.318
0.326
0.335
0.343
0.351
0.359
0.367
0.375
0.384
0.392
0.400
0.408
MIN.
E-3
HYSTERESIS RANGE (V)
V
HYS
MAX.
0.008
0.009
0.010
0.011
0.012
0.013
0.014
0.015
0.016
0.017
0.018
0.019
0.020
0.021
0.022
0.023
0.024
0.026
0.027
0.028
0.029
0.030
0.031
0.032
0.033
0.034
0.035
0.036
0.037
0.038
0.039
0.040
0.041
0.042
0.043
0.044
0.045
0.046
0.047
0.048
0.049
0.050
0.051
MIN.
E-4
SENSE RESISTANCE (MΩ)
R
SEN
TYP.
10
20
0
13
24
15
28
PS037301-0615
PRELIMINARY
3
Product Specification
IXD5118
PIN CONFIGURATION
USP-4
(BOTTOM VIEW)
SOT-25
(TOP VIEW)
PIN ASSIGNMENT
PIN NUMBER
SSOT-24
USP-4
1
1
5
2
4
3
3
4
2
5
PIN NAME
V
OUT
C
D
VSEN
V
IN
V
SS
FUNCTIONS
Output Voltage (Detect “LOW”)
Delay Capacitor Connection
Sense Voltage Input
Power Input
Ground (USP-4 uses power dissipation pin as a Ground pin)
BLOCK DIAGRAMS
IXD5118CxxA
IXD5118NxxA
IXD5118CxxB
IXD5118NxxB
Diodes inside the circuits are ESD protection diodes and parasitic diodes.
PS037301-0615
PRELIMINARY
4
Product Specification
IXD5118
BASIC OPERATION
Operation of the IXD5118 in a typical application circuit is exlained by the timing diagram shown below.
At initial state, the sufficiently high voltage (6.0 V MAX.) applies to the sense pin, and the delay capacitor C
D
is
charged to the power supply input voltage (1.0V ≤ V
IN
≤ 6.0 V). While the sense pin voltage (V
SEN
) starts
dropping, the output voltage V
OUT
remains at “High” level equal V
IN
as long, as the detect voltage V
SEN
> V
DF
.
(Output voltage “High” level is equal pull-up voltage for IXD518N version.)
The sense pin voltage keeps dropping and becomes equal to the detect voltage (V
SEN
=V
DF
), Comparator (see
Block Diagram) trips, a N-channel transistor M1 turns ON, discharging the delay capacitor C
D
, and the output
voltage changes state to the “Low” level, equal V
SS
.
The detect delay time t
DF
is defined as time from the moment, when V
SEN
= V
DF
to the moment, when V
OUT
changes state to “Low” level (t
DF0
, when the C
D
pin is open).
The output voltage maintains at the “Low” level as long as the sense pin voltage is below the release voltage
(V
SEN
< V
DF
+V
HYS
), and the delay capacitor C
D
remains discharged to the ground voltage level.
When the sense pin voltage increases to the release voltage level (V
SEN
= V
DF
+ V
HYS
), the N-channel transistor
M1 turns OFF, and the delay capacitor C
D
start charging via a delay resistor R
DEL
.
The C
D
pin voltage (V
CD
) continues rising up to the C
D
pin threshold voltage (V
TCD
), because the sense pin
voltage is higher than the release voltage.
The time constant of the C
D
pin voltage is
= R
DEL
C
D
, so the Release Delay Time (t
DR
) can be determined as
t
DR
= -R
DEL
×
C
D
×
ln(1-V
TCD
/V
IN
)
…(1)
The Release Delay time can also be calculated with the formula (2), because R
DEL
= 2.0 MΩ (TYP.) and the
delay C
D
pin threshold voltage is V
IN
/2 (TYP.)
t
DR
= R
DEL
×
C
D
×
0.69
…(2)
As an example, presuming that the delay capacitance is 0.68 μF, t
DR
is :
6
-6
t
DR
=2.0
×10 ×0.68 ×10 ×0.69
= 938 (ms)
Note that the release delay time may be remarkably short, if the delay capacitor C
D
did not discharge to the
ground (V
SS
) level, because of short time in state
.
When the C
D
pin voltage reaches threshold level (V
CD
= V
TCD
), the inverter will change state of the output. As a
result, the output voltage changes into the “High” (V
IN
) state.
While the sense voltage is higher than the detect voltage (V
SEN
> V
DF
), the delay capacitor charges up to the
input voltage level. The output voltage maintains the “High” level equal V
IN
.
PS037301-0615
PRELIMINARY
5
京公网安备 11010802033920号
EEWORLD
