BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
512K X 16 bit
DESCRIPTION
BS616UV8010
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 15mA (Max.) operating current
I-grade : 20mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=2V
-10
100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8010 is available in 48-pin BGA package.
PRODUCT FAMILY
SPEED
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
(ns)
Vcc=2 V Vcc=2V Vcc=3V Vcc=2V Vcc=3V
BS616UV8010BC
BS616UV8010BI
+0 C to +70 C 1.8V ~ 3.6V 70 / 100
O
O
-
40 C to +85 C 1.8V ~ 3.6V 70 / 100
O
O
2uA
4uA
3uA
6uA
15mA
20mA
20mA
25mA
BGA
-
48
-
0810
BGA
-
48
-
0810
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
A 18
2
OE
UB
D10
D11
D12
D13
NC
.
A8
3
A0
A3
A5
A17
VSS
A14
A 12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
WE
A11
6
CE2
D0
D2
VCC
VSS
D6
D7
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
4096
D0
16
Data
Input
Buffer
16
Column I/O
.
.
.
.
D15
CE2
CE1
WE
OE
UB
LB
.
.
.
.
Write Driver
Sense Amp
256
Column Decoder
16
Data
Output
16
Buffer
16
Control
Address Input Buffer
NC
A11 A10 A9 A8 A7 A6 A5 A18
Vcc
Gnd
48-Ball CSP top View
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
R0201-BS616UV8010
1
Revision 2.4
April 2002
BSI
PIN DESCRIPTIONS
BS616UV8010
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
Name
A0-A18 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Gnd
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE1
H
X
L
L
CE2
X
L
H
H
WE
X
X
H
H
OE
X
X
H
L
LB
X
X
X
L
H
L
L
Write
L
H
L
X
H
L
UB
X
X
X
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5 to
Vcc+0.5
-40 to +125
-60 to +150
1.0
20
UNITS
V
O
OPERATING RANGE
AMBIENT
RANGE
TEMPERATURE
Commercial
Industrial
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
1.8V ~ 3.6V
1.8V ~ 3.6V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
C
IN
V
IN
=0V
10
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
C
DQ
V
I/O
=0V
12
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
1. This parameter is guaranteed and not tested.
maximum rating conditions for extended periods may affect reliability.
R0201-BS616UV8010
pF
pF
2
Revision 2.4
April 2002
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
I
CC
I
CCSB
BS616UV8010
TEST CONDITIONS
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
MIN. TYP.
-0.5
-0.5
1.4
2.0
--
--
--
--
1.6
2.4
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.4
0.5
(1)
MAX.
0.6
0.8
Vcc+0.2
Vcc+0.2
UNITS
V
V
uA
uA
V
V
mA
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1 = V
IH
, or CE2 = V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 1mA
Vcc = Min, I
OH
= -0.5mA
Vcc= max, CE1 = V
IL
and CE2 =
V
IH
, I
DQ
= 0mA, F = Fmax
(3)
Vcc= max, CE1 = V
IH
or CE2 =
V
IL
, I
DQ
= 0mA
Vcc= max,CE1
Vcc-0.2V, or
CE2
0.2V, V
IN
Vcc - 0.2V
IN
0.2V
or V
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
1
1
0.4
0.4
--
--
15
20
0.6
1
2
3
I
CCSB1
Standby Current-CMOS
uA
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CE1
V
IN
CE1
V
IN
TEST CONDITIONS
Vcc - 0.2V or CE2 0.2V
Vcc - 0.2V or V
IN
0.2V
Vcc - 0.2V or CE2 0.2V
Vcc - 0.2V or V
IN
0.2V
MIN. TYP.
1.5
--
0
T
RC (2)
--
(1)
MAX.
--
2
--
--
UNITS
V
uA
ns
ns
0.2
--
--
See Retention Waveform
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE1
≥
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
1.5V
Vcc
t
CDR
t
R
CE2
0.2V
CE2
R0201-BS616UV8010
V
IL
V
IL
3
Revision 2.4
April 2002
BSI
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
WAVEFORM
INPUTS
BS616UV8010
KEY TO SWITCHING WAVEFORMS
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MUST BE
STEADY
MAY CHANGE
FROM H TO L
1333
Ω
AC TEST LOADS AND WAVEFORMS
2V
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
1333
Ω
2V
OUTPUT
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
,
5PF
2000
Ω
INCLUDING
JIG AND
SCOPE
2000
Ω
FIGURE 1A
THEVENIN EQUIVALENT
800
Ω
FIGURE 1B
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
←
→
←
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C, Vcc=2V)
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
(CE2,CE1)
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
BS616UV8010-70
MIN. TYP. MAX.
BS616UV8010-10
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
70
--
(CE1)
(CE2)
(LB,UB)
(CE2,CE1)
(LB,UB)
--
--
--
--
10
10
10
0
0
0
10
(LB,UB)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
35
--
--
--
35
35
30
--
100
--
--
--
--
--
15
15
15
0
0
0
15
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
50
50
--
--
--
40
40
35
--
NOTE :
1. t
BA
is 35ns/50ns (@speed=70ns/100ns) with address toggle .
t
BA
is 70ns/100ns (@speed=70ns/100ns) without address toggle .
R0201-BS616UV8010
4
Revision 2.4
April 2002
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616UV8010
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE2
t
t
ACS2
ACS1
CE1
t
D
OUT
(5)
CLZ
(5)
t
CHZ
READ CYCLE3
(1,4)
ADDRESS
t
RC
t
OE
AA
t
CE2
OE
t
OH
t
t
t
t
(5)
CLZ
ACS2
CE1
OLZ
ACS1
t
t
OHZ
CHZ
(5)
(1,5)
LB,UB
t
BE
t
t
BA
BDO
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2 = V
IH.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616UV8010
5
Revision 2.4
April 2002
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