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5962-9318709H4C

Description
SRAM Module, 128KX32, 20ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Categorystorage    storage   
File Size374KB,34 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

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5962-9318709H4C Overview

SRAM Module, 128KX32, 20ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9318709H4C Parametric

Parameter NameAttribute value
Objectid1820273827
Parts packaging codePGA
package instructionPGA,
Contacts66
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time20 ns
Other featuresUSER CONFIGURABLE AS 512K X 8
Spare memory width16
JESD-30 codeS-CPGA-P66
JESD-609 codee4
length27.3 mm
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals66
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height4.34 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width27.3 mm
REVISIONS
LTR
E
DESCRIPTION
Figure 1: For case outlines 4 and 5 changed the dimension D3 min
and max limits to 1.020 and 1.060 inches. For case outlines 4 and 5
changed dimension A min limit to .135 inches. For case outlines 4
and 5 changed dimension L min limit to .132 inches. -sld
Table I; changed the max limit for I
CC32
for device types 05, 06, 07,
and 08 from 520 mA to 600 mA. Changed the max limit for I
CCDR1
for
device types 05 through 10 from 10.4 mA to 11.6 mA. -sld
Added device type 11. Added vendor CAGE 0EU86 for device types
05 through 09. -sld
Figure 1; changed the maximum limit for dimension D3 from 1.060
inches to 1.086 inches for case outlines 4 and 5. -sld
Added note to paragraph 1.2.2 and table I regarding the 4 transistor
design. Added footnote 3 for case outlines U, T, X, and Y on the
bulletin page. Redrew entire document. -sld
Added device types 12 through 18. -sld
Updated drawing. -gz
Update drawing to the latest requirements of MIL-PRF-38534. –gc
DATE (YR-MO-DA)
98-04-06
APPROVED
K. A. Cottongim
F
98-07-13
K. A. Cottongim
G
H
J
99-08-27
00-02-07
00-11-14
Raymond Monnin
Raymond Monnin
Raymond Monnin
K
L
M
01-11-13
07-04-16
18-01-23
Raymond Monnin
Robert M. Heber
Charles F. Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
M
15
M
16
M
17
M
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
M
19
M
20
M
21
M
1
M
22
M
2
M
23
M
3
M
24
M
4
M
25
M
5
M
26
M
6
M
7
M
8
M
9
M
10
M
11
M
12
M
13
M
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.dla.mil/landandmaritime
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, DIGITAL, STATIC
RANDOM ACCESS MEMORY, CMOS, 128K x
32-BIT
DRAWING APPROVAL DATE
94-06-24
REVISION LEVEL
M
SIZE
A
SHEET
CAGE CODE
67268
1 OF
26
5962-93187
5962-E208-18
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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