2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM)
SDA 9253
Preliminary Data
Features
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CMOS IC
212
×
64
×
16
×
12-bit organization
Triple port architecture
One 16
×
12-bit input shift register
Two 16
×
12-bit output shift registers
Shift registers independently and simultaneously
accessible
Continuous data flow even at maximum speed
40-MHz shift rate – 0.96-Gbit/s total data rate
All inputs and outputs TTL-compatible
Tristate outputs
Random access of groups of 16
×
12 bits for a wide range
of applications
Refresh-free operation possible
5 V
±
10 % power supply
0 … 70
°C
operating temperature range
Low power dissipation: 700 mW active, 28 mW standby
Suitable for all common TV standards
Allows flicker and noise reduction simultaneously
with only one field memory
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
P-MQFP-64-1
Type
SDA 9253
Ordering Code
Q67101-H5171
Package
P-MQFP-64-1
Semiconductor Group
1
1998-01-30
SDA 9253
Functional Description
The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate
video applications. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the
storage of 12-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality
(13.5-MHz basic sample rate) or 12-bit planes of parts of a HDTV field. The memory is fabricated
using the same CMOS technology used for 4-Mbit standard dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16
×
12-bit
input shift register C to an addressed location of the memory array and from the memory array to
one of the 16
×
12-bit output shift registers A or B is controlled by the serial row-(SAR) and column
address (SAC) which contains the desired column address and an instruction code (mode bits) for
transfer and refresh.
Circuit Description
Memory Architecture
As shown in the block diagram, the TV-SAM comprises 192 memory arrays, which are accessed in
parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the
192 arrays can be randomly addressed, reading or writing 16
×
12 bits at a time. To obtain the
extremely high data rate at the 12-bit wide data input (SDC) and outputs (SQA, SQB), a parallel to
serial conversion is done using shift registers of 16-bit length and 12-bit width. In this way the
memory speed is increased by a factor of 16. (This is independent on the number of ports if the total
data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16
×
12-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.
Semiconductor Group
2
1998-01-30
SDA 9253
Data Input (SDC, SCB)
Data are shifted in through the serial port C (SDC0, …, SDC11) at the rising edge of the shift clock
SCB. After 16 clock pulses the data have to be transferred from shift register C to latch C. If more
than 16 clock pulses occur before latching the data, only the last sixteen 12-bit data values are
accepted.
Data Transfer from Shift Register C to Latch C (WT)
The contents of the shift register C are transferred to latch C at the falling edge of the write transfer
signal WT. If the timing restrictions between WT and the clock SCB are respected, a continuous
data flow at input SDC is possible without loosing data. This transfer operation may be
asynchronous to all other transfer operations except for a small forbidden window conditioned by
the latch C to memory transfer, see
diagram 4.
Write Transfer from Latch C to Memory (RE)
The data of latch C are transferred to the preaddressed location of the memory array at the rising
edge of RE, if the mode bits were set to H (M1) and L (M0), see “Addressing and Mode Control.”
Addressing and Mode Control (SAR, SAC, SCAD, RE)
The serial 8-bit row address SAR and the 8-bit column address/mode code SAC are serially shifted
into the TV-SAM (LSB first) at rising edge of the address clock SCAD. After 8 SCAD cycles, the
falling edge of RE internally latches SAR and SAC. The column address itself needs only 6 bits. The
last 2 bits of SAC are defined as mode bits and determine the read/write and refresh operation of
the memory arrays to be triggered by the RE signal.
Mode Bit M1
L
L
H
H
Mode Bit M0
L
H
L
H
Operation
Read transfer from memory to latch A
Read transfer from memory to latch B
Write transfer from latch C to memory
Refresh with internal row address
Read Transfer from Memory to Latch A or B (RE)
Memory data from a preaddressed location are transferred to latch A or B at the falling edge of RE,
depending on the mode control bits, see “Addressing and Mode Control”.
Data Transfer from Latch A to Shift Register A (RA)
The contents of latch A are transferred to shift register A at the falling edge of the read transfer
signal RA. If the timing restrictions between RA and the shift clock SCA are taken into account, a
continuous data flow at output SQA without interrupts is possible. This transfer operation is
independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch A transfer.
Semiconductor Group
3
1998-01-30
SDA 9253
Data Transfer from Latch B to Shift Register B (RB)
The contents of latch B are transferred to shift register B at the falling edge of the read transfer
signal RB. If the timing restrictions between RB and the shift clock SCB are taken into account, a
continuous data flow at output SQB without interrupts is possible. This transfer operation is
independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch B transfer.
Data Output A (SQA, SCA, OEA)
Data is shifted out through the serial port A (SQA0 … SQA11) at the rising edge of the shift clock
SCA. After 16 clock cycles new data have to be transferred from latch A to shift register A.
Otherwise data values are cyclically repeated.
Via the output enable OEA the output buffers can be switched into tristate.
The shift clock SCA may be completely independent on the shift clock for port B and C (SCB).
Data Output B (SQB, SCB, OEB)
Data is shifted out through the serial port B (SQB0 … SQB11) at the rising edge of the shift clock
SCB. After 16 clock cycles new data have to be transferred from latch B to shift register B.
Otherwise data values are cyclically repeated. The shift clock SCB is also used for the input port C.
Via the output enable OEB the output buffers can be switched into tristate.
Refresh
Either 256 refresh cycles or read/write cycles on 212 consecutive row addresses beginning with
address 0 have to be executed within an 16 ms interval to maintain the data in the memory arrays.
A refresh cycle is determined by the mode control bits, see “Addressing and Mode Control”. In the
refresh mode, the row and column addresses are ignored.
Initialization
The device incorporates an on-chip substrate bias generator as well as dynamic circuitry. Therefore
an initial pause of 200
µs
is required after power on, followed by eight RE-cycles before proper
device operation is achieved.
Semiconductor Group
4
1998-01-30
SDA 9253
Typical Memory Cycle Sequence
A typical application of the TV-SAM is a real-time interfield image processing combined with flicker
reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via
port C and B and by simultaneously reading port A with 27-MHz double speed clock. A main cycle
of 4 consecutive RE cycles of transfer is needed:
1st.
2nd.
3rd.
4th.
RE-cycle:
RE-cycle:
RE-cycle:
RE-cycle:
Read transfer from memory to latch A
Read transfer from memory to latch B
Same as 1st. RE cycle
Write transfer from latch C to memory
Each transfer cycle is preceeded by an address cycle as shown in the diagram page 6:
For the clock rates mentioned this means a serial cycle time of 74 ns at port B and C and 37 ns at
port A. The addressing cycle time for each port is given by 16 times the serial data rate. Thus we
have an addressing cycle time of approx. 1184 ns for port B and port C. The address for port A must
be loaded every 592 ns. Since all addresses are shifted in sequentially, a RE cycle time of approx.
296 ns is necessary.
The beginning of a block of 16 serial data at port A or B is determined by RA and RB, respectively.
The end of the serial input data block at port C is controlled by WT. Since RA, RB and WT can be
independently chosen (except for small forbidden time windows when memory transfers are
executed), the serial data streams can be shifted against each other without influencing the RE
cycles.
Semiconductor Group
5
1998-01-30
DSP and ARM Processors
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