74ALVCH16374DTR datasheet, PDF

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74ALVCH16374DTR: DescriptionLowâVoltage 16âBit DâType FlipâFlop; Categorylogic logic; File Size280KB，11 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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74ALVCH16374DTR Overview

LowâVoltage 16âBit DâType FlipâFlop

74ALVCH16374DTR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP48,.3,20
Contacts	48
Reach Compliance Code	_compli
series	ALVC/VCX/A
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	12.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
Maximum Frequency@Nom-Su	150000000 Hz
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
power supply	3.3 V
Prop。Delay @ Nom-Su	4.2 ns
propagation delay (tpd)	0.25 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	6.1 mm
Base Number Matches	1

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74ALVCH16374

Low−Voltage 16−Bit D−Type

Flip−Flop with Bus Hold

1.8/2.5/3.3 V

(3−State, Non−Inverting)

The 74ALVCH16374 is an advanced performance, non−inverting

16−bit D−type flip−flop. It is designed for very high−speed, very

low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The

VCXH16374 is byte controlled, with each byte functioning

identically, but independently. Each byte has separate Output Enable

and Clock Pulse inputs. These control pins can be tied together for full

16−bit operation.

The 74ALVCH16374 consists of 16 edge−triggered flip−flops with

individual D−type inputs and 3.6 V−tolerant 3−state outputs. The

clocks (CPn) and Output Enables (OEn) are common to all flip−flops

within the respective byte. The flip−flops will store the state of

individual D inputs that meet the setup and hold time requirements on

the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the

contents of the flip−flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. The OE input level

does not affect the operation of the flip−flops. The data inputs include

active bushold circuitry, eliminating the need for external pull−up

resistors to hold unused or floating inputs at a valid logic state.

http://onsemi.com

MARKING DIAGRAM

74ALVCH16374DT

AWLYYWW

TSSOP−48

DT SUFFIX

CASE 1201

Location

= Assembly

= Wafer Lot

= Year

= Work Week

PIN NAMES

Pins

OEn

CPn

D0−D15

O0−O15

Function

Output Enable Inputs

Clock Pulse Inputs

Inputs

Outputs

•

Designed for Low Voltage Operation: V

= 1.65

−

3.6 V

•

3.6 V Tolerant Inputs and Outputs

•

High Speed Operation: 3.6 ns max for 3.0 to 3.6 V

•

4.5 ns max for 2.3 to 2.7 V

7.8 ns max for 1.65 to 1.95 V

Static Drive:

±24

mA Drive at 3.0 V

±12

mA Drive at 2.3 V

±4

mA Drive at 1.65 V

Supports Live Insertion and Withdrawal

Includes Active Bushold to Hold Unused or Floating Inputs at a Valid

Logic State

OFF

Specification Guarantees High Impedance When V

= 0 V

†

Near Zero Static Supply Current in All Three Logic States (40

mA)

Substantially Reduces System Power Requirements

Latchup Performance Exceeds

±250

mA @ 125°C

ESD Performance: Human Body Model >2000V; Machine Model >200V

Second Source to Industry Standard 74ALVCH16374

ORDERING INFORMATION

Device

74ALVCH16374DTR

Package

TSSOP

Shipping

2500 / Reel

†To ensure the outputs activate in the 3−state condition, the output enable pins

should be connected to V

through a pull−up resistor. The value of the resistor is

determined by the current sinking capability of the output connected to the OE pin.

Semiconductor Components Industries, LLC, 2006

June, 2006

−

Rev. 3

Publication Order Number:

74ALVCH16374/D

74ALVCH16374DTR Related Products

	74ALVCH16374DTR	74ALVCH16374
Description	LowâVoltage 16âBit DâType FlipâFlop	LowâVoltage 16âBit DâType FlipâFlop

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