74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev. 1 — 16 July 2012
Product data sheet
1. General description
The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL).
The 74HC138-Q100; 74HCT138-Q100 decoder accepts three binary weighted address
inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW
outputs (Y0 to Y7).
The 74HC138-Q100; 74HCT138-Q100 features three enable inputs: two active LOW
(E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are
LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the 74HC138-Q100;
74HCT138-Q100 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138-Q100;
74HCT138-Q100 ICs and one inverter.
The 74HC138-Q100; 74HCT138-Q100 can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data input and the remaining enable
inputs as strobes. Not used enable inputs must be permanently tied to their appropriate
active HIGH- or LOW-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Demultiplexing capability
Multiple input enable for easy expansion
Complies with JEDEC standard no. 7A
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC138D-Q100
74 HCT138D-Q100
74HC138PW-Q100
74HCT138PW-Q100
74HC138BQ-Q100
74HCT138BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
Y0
1
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
4
5
6
E1
E2
E3
Y4
Y5
Y6
Y7
mna370
15
14
13
12
11
10
9
7
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
2
3
4
5
6
E1
E2
E3
mna372
Fig 1.
Logic symbol
Fig 2.
Functional diagram
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2012
2 of 18
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
A2
Y7
Y6
A1
Y5
A0
Y4
E1
Y3
E2
Y2
E3
Y1
Y0
001aae059
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74HC138/Q100
74HCT138/Q100
74HC138/Q100
74HCT138/Q100
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
aaa-003153
terminal 1
index area
A1
2
3
4
5
6
7
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
Y6
9
aaa-003154
© NXP B.V. 2012. All rights reserved.
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
Y6
A2
E1
E2
E3
Y7
GND
(1)
8
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 4.
Pin configuration SO16 and TSSOP16
Fig 5.
Pin configuration DHVQFN16
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 16 July 2012
GND
1
A0
3 of 18
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
5.2 Pin description
Table 2.
Symbol
A0, A1, A2
E1, E2
E3
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
GND
V
CC
Pin description
Pin
1, 2, 3
4, 5
6
15, 14, 13, 12, 11, 10, 9, 7
8
16
Description
address input A0, A1, A2
enable input E1, E2 (active LOW)
enable input E3 (active HIGH)
output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (active LOW)
ground (0 V)
positive supply voltage
6. Functional description
Table 3.
Control
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
L
L
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Function table
[1]
Input
A2
X
A1
X
A0
X
Output
Y7
H
Y6
H
Y5
H
Y4
H
Y3
H
Y2
H
Y1
H
Y0
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2012
4 of 18
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
[1]
Max
+7
20
20
25
50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC138-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT138-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2012
5 of 18
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