Low Voltage, 1:15 Differential PECL Clock
Divider and Fanout Buffer
8T33FS6222
DATA SHEET
General Description
The 8T33FS6222 is a bipolar monolithic differential clock fanout
buffer. Designed for most demanding clock distribution systems, the
8T33FS6222 supports various applications that require the
distribution of precisely aligned differential clock signals. Using SiGe
technology and a fully differential architecture, the device offers very
low skew outputs and superior digital signal characteristics. Target
applications for this clock driver is high performance clock distribution
in computing, networking and telecommunication systems.
Features
• Fifteen differential PECL outputs (four output banks)
• Two selectable differential PECL inputs
• Selectable ÷1 or ÷2 frequency divider
• Supports DC to 2GHz input frequency
• Single 3.3V or 2.5V supply
• Standard 52-Lead TQFP package with exposed pad for enhanced
thermal characteristics
• Supports industrial temperature range
• Lead-free RoHS 6 packaging
Functional Description
The 8T33FS6222 is designed for low skew clock distribution systems
and supports clock frequencies up to 2GHz. The CLK0 and CLK1
inputs can be driven by PECL compatible signals. Each of the four
output banks of two, three, four and six differential clock output pairs
can be independently configured to distribute the input frequency or
2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and
CLK_SEL are asychronous control inputs. Any changes of the
control inputs require a MR pulse for resynchronization of the 2
outputs. For the functionality of the MR control input, see
Figure 4.Functional Diagram.
In order to meet the tight skew specification of the device, both
outputs of a differential output pair should be terminated, even if only
one output is used. In the case where not all ten outputs are used,
the output pairs on the same package side as the parts being used
on that side should be terminated.
The 8T33FS6222 can be operated from a single 3.3V or 2.5V supply.
.
8T33FS6222 REVISION 1 2/2/15
1
©2015 Integrated Device Technology, Inc.
8T33FS6222 DATA SHEET
.
FSELA
nQC0
nQC1
nQC2
V
CC
V
CC
CLK0
nCLK0
V
EE
V
CC
CLK1
nCLK1
V
EE
CLK_SEL
V
EE
FSELB
FSELC
0
1
QA1
1
39 38 37 36 35 34 33 32 31 30 29 28 27
1
2
0
1
QB0
QB1
QB2
QC0
QC1
V
CC
nQB2
QB2
nQB1
QB1
nQB0
QB0
V
CC
nQA1
QA1
nQA0
QA0
V
CC
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
10 11 12 13
V
CC
NC
NC
V
CC
V
EE
0
nQC3
QA0
QC0
QC1
QC2
QC3
26
25
24
23
22
21
QD0
nQD0
QD1
nQD1
QD2
nQD2
QD3
nQD3
QD4
nQD4
QD5
nQD5
V
CC
0
1
8T33FS6222
20
19
18
17
16
15
14
QC2
QC3
QD0
0
V
EE
QD1
QD2
1
V
EE
QD3
QD4
QD5
V
EE
V
BB
MR
FSELA
FSELB
CLK_SEL
V
CC
V
BB
FSELC
FSELD
52-pin, 10mm x 10mm TQFP Package
Figure 1. 8T33FS6222 Logic Diagram
Figure 2. 52-Lead Package Pin Assignment
LOW VOLTAGE, 1:15 DIFFERENTIAL PECL CLOCK
DIVIDER AND FANOUT BUFFER
2
FSELD
CLK0
nCLK0
CLK1
MR
nCLK1
REVISION 1 2/2/15
V
EE
8T33FS6222 DATA SHEET
Pin Description and Characteristics
Table 1. Pin Description Table
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
REVISION 1 2/2/15
Name
V
CC
MR
FSELA
FSELB
CLK0
nCLK0
CLK_SEL
CLK1
nCLK1
V
BB
FSELC
FSELD
V
EE1
V
CC
nQD5
QD5
nQD4
QD4
nQD3
QD3
nQD2
QD2
nQD1
QD1
nQD0
QD0
V
CC
NC
NC
V
CC
nQC3
QC3
Power
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Unused
Unused
Power
Output
Output
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Type
Description
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Reset.
Selection output frequency divider for Bank A.
Selection output frequency divider for Bank B.
Differential reference clock signal input.
Differential reference clock signal input.
Clock reference select input.
Alternative differential reference clock signal input.
Alternative differential reference clock signal input.
Reference voltage output for single ended PECL operation.
Selection output frequency divider for Bank C.
Selection output frequency divider for Bank D.
Negative power supply.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Bank D differential output.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
No internal connection.
No internal connection.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Bank C differential output.
Bank C differential output.
3
LOW VOLTAGE, 1:15 DIFFERENTIAL PECL CLOCK
DIVIDER AND FANOUT BUFFER
8T33FS6222 DATA SHEET
Table 1. Pin Description Table
Number
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
ePAD
Name
nQC2
QC2
nQC1
QC1
nQC0
QC0
V
CC
V
CC
nQB2
QB2
nQB1
QB1
nQB0
QB0
V
CC
nQA1
QA1
nQA0
QA0
V
CC
V
EE_EP
Power
Power
Output
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Type
PECL
PECL
PECL
PECL
PECL
PECL
Description
Bank C differential output.
Bank C differential output.
Bank C differential output.
Bank C differential output.
Bank C differential output.
Bank C differential output.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Bank B differential output.
Bank B differential output.
Bank B differential output.
Bank B differential output.
Bank B differential output.
Bank B differential output.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Bank A differential output.
Bank A differential output.
Bank A differential output.
Bank A differential output.
Power supply. All V
CC
pins must be connected to the positive power
supply for correct DC and AC operation.
Exposed pad of package. Connect to ground.
NOTE 1. In PECL mode (positive power supply mode), V
EE
is connected to GND (0V) and V
CC
is either +3.3 V or +2.5 V. The input and output
levels are referenced to the most positive supply (V
CC
).
Table 2. Function Table
Control Pin
FSELA (asynchronous)
FSELB (asynchronous)
FSELC (asynchronous)
FSELD (asynchronous)
CLK_SEL (asynchronous)
MR (asynchronous)
0
1
1
1
1
CLK0
Active
1
2
2
2
2
CLK1
Reset. Qx = L and nQx = H
LOW VOLTAGE, 1:15 DIFFERENTIAL PECL CLOCK
DIVIDER AND FANOUT BUFFER
4
REVISION 1 2/2/15
8T33FS6222 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability
Table 3. Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
T
FUNC
T
J
HBM
CDM
Characteristics
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Functional Temperature Range
Operating Junction Temperature
ESD Human Body Model
1
ESD Charged Device Model
1
-65
T
A
= -40
Condition
Min
-0.3
-0.3
-0.3
Max
3.6
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
T
A
= +85
125
2000
500
Unit
V
V
V
mA
mA
°C
°C
°C
V
V
NOTE 1. According to JEDEC/JS-001-2012/JESD22-C101E.
REVISION 1 2/2/15
5
LOW VOLTAGE, 1:15 DIFFERENTIAL PECL CLOCK
DIVIDER AND FANOUT BUFFER
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