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ICS574

Description
Zero Delay, Low Skew Buffer
File Size138KB,8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

ICS574 Overview

Zero Delay, Low Skew Buffer

DATASHEET
ZERO DELAY, LOW SKEW BUFFER
Description
The ICS574 is a low jitter, low-skew, high performance
PLL-based zero delay buffer for high speed applications.
Based on IDT’s proprietary low jitter Phase Locked Loop
(PLL) techniques, the device provides four low skew
outputs at speeds up to 160 MHz at 3.3 V. When one of the
outputs is connected directly to FBIN, the rising edge of
each output is aligned with the rising edge of the input
clock. External delay elements connected in the feedback
loops will cause the outputs to occur before the inputs by
the amount of propagation delay of the external element.
ICS574
Features
Packaged in 8 pin narrow SOIC, Pb (lead) free
Zero input-to-output delay
Four 1X outputs
Output to output skew is less than 150 ps
Output clocks up to 160 MHz at 3.3 V
External feedback path for output edge placement
Spread Smart™ technology works with spread spectrum
clock generators
TTL levels at 3.3 V
Full CMOS outputs with 18 mA output drive capability at
Advanced, low power, sub-micron CMOS process
Operating voltage from 3.0 to 5.5 V
Industrial temperature version available
Block Diagram
CLK1
FBIN
CLKIN
CLK2
PLL
CLK3
CLK4
IDT™/ ICS™
ZERO DELAY, LOW SKEW BUFFER
1
ICS574
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