SL74HCT163
Presettable Counters
High-Performance Silicon-Gate CMOS
The SL74HCT163 is identical in pinout to the LS/ALS163. The
SL74HCT163 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The SL74HCT163 is programmable 4-bit synchronous counter that
feature parallel Load, synchronous Reset, a Carry Output for cascading
and count-enable controls.
The SL74HCT163 is binary counter with synchronous Reset.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
ORDERING INFORMATION
SL74HCT163N Plastic
SL74HCT163D SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16 =V
CC
PIN 8 = GND
Inputs
Reset
L
H
H
H
H
X
Load
X
L
H
H
H
X
Enable
P
X
X
X
L
H
X
FUNCTION TABLE
Outputs
Enable
T
X
X
L
X
H
X
Clock
Q0
L
P0
Q1
L
P1
Q2
L
P2
Q3
L
P3
Function
Reset to “0”
Preset Data
No count
No count
Count
No count
No change
No change
Count up
No change
X=don’t care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enable T
•
Q0
•
Q1
•
Q2
•
Q3
SLS
System Logic
Semiconductor
SL74HCT163
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HCT163
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
4.0
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
40
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
160
µA
µA
V
Unit
V
IH
V
IL
V
OH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
6.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
V
V
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
6.0 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Additional Quiescent
Supply Current
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
V
IN
= 2.4 V, Any One Input
V
IN
=V
CC
or GND,
Other Inputs
I
OUT
=0µA
∆I
CC
≥-55°C
25°C to
125°C
2.4
mA
5.5
2.9
SLS
System Logic
Semiconductor
SL74HCT163
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
, t
THL
C
IN
Maximum Propagation Delay, Clock to Ripple
Carry Out (Figures 1,6)
Maximum Output Transition Time, Any Output,
(Figures 1 and 6)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Gate)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
+∆I
CC
V
CC
Parameter
Maximum Clock Frequency (Figures 1,6)
Maximum Propagation Delay, Clock to Q
(Figures 1,6)
Maximum Propagation Delay, Enable T to Ripple
Carry Out (Figures 2,6)
25
°C
to
-55°C
30
34
41
32
39
35
43
15
10
≤85°C
24
43
51
40
49
44
54
19
10
≤125°C
20
51
62
48
59
53
65
22
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
Typical @25°C,V
CC
=5.0 V
60
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
su
t
su
t
su
t
su
t
h
t
h
t
h
t
h
t
rec
t
w
t
w
t
r,
t
f
Parameter
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
Minimum Setup Time, Load to Clock (Figure 4)
Minimum Setup Time, Reset to Clock (Figure 3)
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 5)
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 4)
Minimum Hold Time, Clock to Load (Figure 4)
Minimum Hold Time, Clock to Reset (Figure 3)
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 5)
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 4)
Maximum Input Rise and Fall Times (Figure 1)
25
°C
to
-55°C
30
27
32
40
10
3
3
3
25
16
16
500
≤85°C
38
34
40
50
13
3
3
3
31
20
20
500
≤125°C
45
41
48
60
15
3
3
3
38
24
24
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SLS
System Logic
Semiconductor
SL74HCT163
SLS
System Logic
Semiconductor
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