V54C3128(16/80/40)4VE
128Mbit SDRAM
3.3 VOLT, TSOP II / FBGA
8M X 16, 16M X 8, 32M X 4
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
Features
-
-
-
-
-
-
-
-
-
-
-
Description
The V54C3128(16/80/40)4VE is a four bank Syn-
chronous DRAM organized as 4 banks x 2Mbit x 16,
4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4. The
V54C3128(16/80/40)4VE achieves high speed data
transfer rates up to 166 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
-
-
-
-
-
-
-
-
-
4 banks x 2Mbit x 16 organization
4 banks x 4Mbit x 8 organization
4 banks x 8Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 54-ball FBGA, 60-ball FBGA, and
54-Pin TSOPII
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
Package Outline
C/S/T
•
•
Access Time (ns)
6
•
•
Power
7
•
•
7PC
•
•
Std.
•
•
Temperature
Mark
Blank
I
V54C3128(16/80/40)4VE Rev. 1.3 June 2011
1
ProMOS TECHNOLOGIES
V54C3128(16/80/40)4VE
Part Number Information
V
ProMOS
5 4
C
3
1 2 8 8 0
ORGANIZATION
& REFRESH
1Mx16, 2K : 1616
4Mx16, 4K : 6516
4
V
E
T
7 5
PC
OTHER
PC
: CL2
TYPE
54 : SDRAM
55 : MOBILE SDRAM
32Mx4, 4K : 12840
16Mx8, 4K : 12880
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
64Mx8, 8K : 51280
8Mx16, 4K : 12816
16Mx16, 8K : 25616
32Mx16, 8K : 51216
BLANK: CL3
TEMPERATURE
BLANK: 0 - 70C
I:
H:
E:
SPEED
I/O
V: LVTTL
REV LEVEL
PACKAGE
LEAD
PLATING
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
T
S
C
B
D
Z
R
E
F
G
H
I
J
K
M
N
P
RoHS
10 : 100MHz
8 : 125MHz
75 : 133MHz
-40 - 85C
-40 - 105C
-40 - 125C
CMOS
BANKS
VOLTAGE
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
7 : 143MHz
6 : 166MHz
5 : 200MHz
4:
3:
2:
1:
3.0V
3.3 V
2.5 V
1.8 V
GREEN PACKAGE
DESCRIPTION
TSOP
60-Ball FBGA
54-BallFBGA
BGA
Die-stacked TSOP
Die-stacked FBGA
* RoHS: Restriction of Hazardous Substances
* Green: RoHS-compliant and Halogen-free
V54C3128(16/80/40)4VE Rev.1.3 June 2011
2
ProMOS TECHNOLOGIES
V54C3128(16/80/40)4VE
128Mb SDRAM Ball Assignment
(54-Ball FBGA)
1
2
X16 devices
3
A
B
C
D
E
F
G
H
J
7
8
9
VDD
DQ1
DQ3
DQ5
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
VDDQ DQ0
VSSQ DQ2
VDDQ DQ4
VSSQ DQ6
Description
Pkg.
Pin Count
DQ10 DQ9 VDDQ
DQ8
NC
VSS
CKE
A9
A6
A4
FBGA
C/K
54
VDD LDQM DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
UDQM CLK
NC
A8
VSS
A11
A7
A5
X8 devices
1
VSS
NC
NC
NC
NC
DQM
NC
A8
VSS
2
3
A
B
C
D
E
F
G
H
J
7
8
9
VDD
NC
NC
NC
NC
WE
CS
A10
VDD
1
VSS
NC
NC
NC
NC
DQM
NC
A8
VSS
2
NC
X4 devices
3
VSSQ
A
B
C
D
E
F
G
H
J
7
VDDQ
8
NC
9
VDD
NC
NC
NC
NC
WE
CS
A10
VDD
DQ7 VSSQ
DQ6 VDDQ
DQ5 VSSQ
DQ4 VDDQ
NC
CLK
A11
A7
A5
VSS
CKE
A9
A6
A4
VDDQ DQ0
VSSQ DQ1
VDDQ DQ2
VSSQ DQ3
VDD
CAS
BA0
A0
A3
NC
RAS
BA1
A1
A2
DQ3 VDDQ
NC
VSSQ
VSSQ DQ0
VDDQ NC
VSSQ DQ1
VDD
CAS
BA0
A0
A3
NC
RAS
BA1
A1
A2
DQ2 VDDQ
NC
CLK
A11
A7
A5
VSS
CKE
A9
A6
A4
V54C3128(16/80/40)4VE Rev. 1.3 June 2011
3
ProMOS TECHNOLOGIES
V54C3128(16/80/40)4VE
128Mb SDRAM Ball Assignment
(60-Ball FBGA)
Description
FBGA
Pkg.
S/J
Pin Count
60
60 Pin WBGA PIN CONFIGURATION
Top View
128 Mb SDRAM Ball Assignment
X16
X8
X4
(60-Ball TrueCSP)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ15
DQ14
VDDQ
DQ11
DQ10
VDDQ
NC
NC
NC
NC
NC
A11
A8
A6
A4
2
VSS
VSSQ
DQ13
DQ12
VSSQ
DQ9
DQ8
VSS
UDQM
CLK
CKE
A9
A7
A5
VSS
1
DQ7
NC
VDDQ
DQ5
NC
VDDQ
NC
NC
NC
NC
NC
A11
A8
A6
A4
2
VSS
VSSQ
DQ6
NC
VSSQ
DQ4
NC
VSS
DQM
CLK
CKE
A9
A7
A5
VSS
1
NC
NC
VDDQ
NC
NC
VDDQ
NC
NC
NC
NC
NC
A11
A8
A6
A4
2
VSS
VSSQ
DQ3
NC
VSSQ
DQ2
NC
VSS
DQM
CLK
CKE
A9
A7
A5
VSS
PIN A1 index
X4
X8
X16
7
VDD
VDDQ
DQ0
NC
VDDQ
DQ1
NC
VDD
WE#
RAS#
NC
BA1
A0
A2
VDD
8
NC
NC
VSSQ
NC
NC
VSSQ
NC
NC
CAS#
NC
CS#
BA0
A10
A1
A3
7
VDD
VDDQ
DQ1
NC
VDDQ
DQ3
NC
VDD
WE#
RAS#
NC
BA1
A0
A2
VDD
8
DQ0
NC
VSSQ
DQ2
NC
VSSQ
NC
NC
CAS#
NC
CS#
BA0
A10
A1
A3
7
VDD
VDDQ
DQ2
DQ3
VDDQ
DQ6
DQ7
VDD
WE#
RAS#
NC
BA1
A0
A2
VDD
8
DQ0
DQ1
VSSQ
DQ4
DQ5
VSSQ
NC
LDQM
CAS#
NC
CS#
BA0
A10
A1
A3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TOP VIEW
V54C3128(16/80/40)4VE Rev. 1.3 June 2011
4
ProMOS TECHNOLOGIES
V54C3128(16/80/40)4VE
128Mb SDRAM Pin Assignment
(54-Pin TSOP-II)
Description
TSOP-II
Pkg.
T/I
Pin Count
54
x16 Configuration
Top View
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CS
RAS
CAS
WE
A
0
–A
11
BA0, BA1
I/O
1
–I/O
16
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3128(16/80/40)4VE Rev. 1.3 June 2011
5
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