32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
SYNCHRONOUS
DRAM MODULE
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
168-pin, dual in-line memory module (DIMM)
PC100- and PC133-compliant
Unbuffered
32MB (4 Meg x 72), 64MB (8 Meg x 72), 128MB (16
Meg x 72)
Supports ECC error detection and correction
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, including CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
Self Refresh Mode: 64ms, 4,096-cycle refresh for
32MB and 64MB; 64ms, 8,192-cycle refresh for
128MB
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Gold edge contacts
MT5LSDT472A – 32MB
MT5LSDT872A(I) – 64MB
MT5LSDT1672A(I) – 128MB
For the latest data sheet, please refer to the Micron
®
Web
site:
www.micron.com/products/modules
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.00in. (25.40mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Operating Temperature Range
Commercial (0°C to +65°C)
Industrial (-40°C to +85°C)
• Frequency / CAS Latency
7.5ns (133 MHz) / CL = 2
7.5ns (133 MHz) / CL = 3
8ns (100 MHz) / CL = 2
NOTE:
Marking
G
Y
1
None
I
2
-13E
-133
-10E
Table 1:
Timing Parameters
SETUP
TIME
1.5
1.5
2ns
HOLD
TIME
0.8
0.8
1ns
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
9ns
–
5.4ns
7.5ns
1. Consult Micron for product availability.
2. Industrial Temperature option available in -133
speed only.
Table 2:
Address Table
32MB
64MB
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0-A11)
512 (A0-A8)
1 (S0#, S2#)
128MB
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0-A12)
512 (A0-A8)
1 (S0#, S2#)
4K
4 (BA0, BA1)
64Mb (4 Meg x 16)
4K (A0-A11)
256 (A0-A7)
1 (S0#, S2#)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
Table 3:
Part Numbers
MODULE DENSITY
32MB
32MB
32MB
32MB
32MB
32MB
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
CONFIGURATION
4 Meg x 72
4 Meg x 72
4 Meg x 72
4 Meg x 72
4 Meg x 72
4 Meg x 72
8 Meg x 72
8 Meg x 72
8Meg x 72
8Meg x 72
8 Meg x 72
8 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
SYSTEM BUS SPEED
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
PART NUMBER
MT5LSDT472AG-13E_
MT5LSDT472AY-13E_
MT5LSDT472AG-133_
MT5LSDT472AY-133_
MT5LSDT472AG-10E_
MT5LSDT472AY-10E_
MT5LSDT872AG-13E_
MT5LSDT872AY-13E_
MT5LSDT872A(I)G-133_
MT5LSDT872A(I)Y-133_
MT5LSDT872AG-10E_
MT5LSDT872AY-10E_
MT5LSDT1672AG-13E_
MT5LSDT1672AY-13E_
MT5LSDT1672A(I)G-133_
MT5LSDT1672A(I)Y-133_
MT5LSDT1672AG-10E_
MT5LSDT1672AY-10E_
NOTE:
The designators for component and PCB revision are the last two characters of each part number. Consult factory for
current revision codes. Example: MT5LSDT1672AG-133B1.
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
Table 4:
Pin Assignment
(168-Pin DIMM Front)
SYMBOL
CB1
V
SS
NC
NC
V
DD
WE#
DQM0
DQM1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CKO
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
SYMBOL
V
SS
NC
S2#
DQM2
DQM3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
PIN SYMBOL
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Table 5:
Pin Assignment
(168-Pin DIMM Back)
106
CB5
107
V
SS
108
NC
109
NC
110
V
DD
111 CAS#
112 DQM4
113 DQM5
114 DNU
115 RAS#
116
V
SS
117
A1
118
A3
119
A5
120
A7
121
A9
122
BA0
123
A11
124
V
DD
125 DNU
126
NC/A12
1
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
V
SS
CKE0
DNU
DQM6
DQM7
DNU
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
NC
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
DNU
NC
SA0
SA1
SA2
V
DD
PIN SYMBOL PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
1. Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module.
Figure 2: Pin Locations (168-Pin DIMM)
Front View
U1
U2
U3
U4
U5
U6
PIN 1
PIN 84
Back View
No Components on This Side of Module
PIN 168
PIN 85
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
Table 6:
PIN Descriptions
SYMBOL
RAS#, CAS#, WE#,
TYPE
Input
DESCRIPTION
Pins may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
27, 111, 115
42, 79
128
30, 45
28, 29, 46, 47, 112, 113,
130, 131
39, 122
33–38, 117–121, 123,
126
(128MB)
83
165-167
82
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95, 97–
101, 103–104, 139–142,
144, 149–151, 153–156,
158–161
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
CK0, CK2
Input
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
CKE0
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including
CK, are disabled during power-down and self refresh modes,
providing low standby power.
S0#, S2#
Input
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
DQMB0–DQMB7
Input
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
A0–A11
Input
Address Inputs: Provide the row address for ACTIVE
(32MB/64MB)
commands, and the column address and auto prcharge bit
A0–A12
(A10) for READ/WRITE commands, to select one location out of
(128MB)
the memory arrary in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW – device
bank selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command.
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
SA0–SA2
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
SDA
Input/Output Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
DQ0–DQ63
Input/Output Data I/Os: Data bus.
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
Table 6:
PIN Descriptions
SYMBOL
CB0–CB7
V
DD
TYPE
Input/Output ECC check bits.
Supply
Power Supply: +3.3V ±0.3V.
DESCRIPTION
Pins may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
21, 22, 52, 53, 105, 106,
136, 137
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
114, 125, 129, 132, 163
24, 25, 31, 44, 48, 50, 51,
61, 62,63, 80, 81, 108,
109, 126 (32MB/64MB),
134, 135, 145-147, 164
V
SS
Supply
Ground.
DNU
NC
–
–
Do Not Use: These pins are not used on these modules, but are
assigned pins on other modules in this product family.
Not Connected: These pins are not connected on these
modules.
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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