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ZVNL120A_15

Description
N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
File Size94KB,4 Pages
ManufacturerDiodes
Websitehttp://www.diodes.com/
Download Datasheet View All

ZVNL120A_15 Overview

N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 200 Volt V
DS
* R
DS(on)
=10Ω
* Low threshold
APPLICATIONS
* Telephone handsets
ZVNL120A
D
G
S
E-Line
TO92 Compatible
SYMBOL
V
DS
I
D
I
DM
V
GS
P
tot
T
j
:T
stg
VALUE
200
180
2
±
20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T
amb
=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at T
amb
=25°C
Operating and Storage Temperature Range
ELECTRICAL CHARACTERISTICS (at T
amb
= 25°C unless otherwise stated).
PARAMETER
Drain-Source Breakdown
Voltage
Gate-Source Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage Drain
Current
On-State Drain Current(1)
Static Drain-Source On-State
Resistance (1)
Forward Transconductance
(1)(2)
Input Capacitance (2)
Common Source Output
Capacitance (2)
Reverse Transfer Capacitance
(2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
SYMBOL MIN. MAX. UNIT CONDITIONS.
BV
DSS
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
200
85
20
7
8
8
20
12
500
10
10
200
0.5
1.5
100
10
100
V
V
nA
µA
µA
mA
mS
pF
pF
pF
ns
ns
ns
ns
V
DD
≈25V,
I
D
=250mA
V
DS
=25 V, V
GS
=0V, f=1MHz
I
D
=1mA, V
GS
=0V
ID=1mA, V
DS
= V
GS
V
GS
=± 20V, V
DS
=0V
V
DS
=200 V, V
GS
=0
V
DS
=160 V, V
GS
=0V, T=125°C
(2)
V
DS
=25 V, V
GS
=5V
V
GS
=5V,I
D
=250mA
V
GS
=3V, I
D
=125mA
V
DS
=25V,I
D
=250mA
(1) Measured under pulsed conditions. Width=300µs. Duty cycle
≤2%
(2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
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