ZXFV4583
SYNC SEPARATOR WITH VARIABLE FILTER
DEVICE DESCRIPTION
The ZXFV4583 provides the ability to separate out
video synchronization signals for a wide variety of TV
and CRT display systems, standard and non-standard.
Flexibility arises from the use of just three external
resistors to adapt to each application. One resistor
controls a fully integrated internal color carrier filter
with variable bandwidth. This filter avoids disturbance
from the color carrier, permitting accurate threshold
slicing for timing extraction.
A second resistor controls the voltage threshold for
loss of signal detection after a time-out interval. The
third resistor controls the timing functions.
DC restoration for displays is facilitated by the Back
Porch synch output, which can be used to drive an
external circuit to clamp the blanking voltage to a fixed
level.
FEATURES AND BENEFITS
•
PAL, NTSC, SECAM
•
Variable filter for optimal accuracy
•
Sync outputs: composite, horizontal, vertical, back
porch, odd/even
•
No-signal detector
•
On chip sample / hold capacitors
•
+5V single supply
•
Default vertical output where there are no
serration pulses
•
Pin and layout compatible with part EL4583 in
SO16N surface mount package
APPLICATIONS
•
Digital image capture
•
Video input systems requiring separation of
picture timing
ORDERING INFORMATION
Part Number
ZXFV4583N16TA
ZXFV4583N16TC
Container
Reel 7″
Reel 13″
Increment
500
2500
•
Video distribution
•
CCTV surveillance
•
Digital multimedia
•
Timing for black level clamp
CONNECTION DIAGRAM
ISSUE 3 - NOVEMBER 2003
1
SEMICONDUCTORS
ZXFV4583
ABSOLUTE MAXIMUM RATINGS
Supply voltage V
CC
Inputs to ground*
Operating temperature range
Storage
Operating ambient junction temperature
-0.5V to +7V
-0.5V to V
CC
+0.5V
-40 C to 85 C
-65 C to +150 C
T
JMAX
150 C**
**The thermal resistance from the semiconductor die to ambient is typically 120 C/W when the SO16 package is
mounted on a PCB in free air. The power dissipation of the device when loaded must be designed to keep the
device junction temperature below T
JMAX.
*During power-up and power-down, these voltage ratings require that signals be applied only when the power
supply is connected.
ELECTRICAL CHARACTERISTICS
V
CC
= 5V, R
SET
= 681k , R
FILT
= 22k , R
NOSIG
= 82k , T
amb
= 25 C unless otherwise stated.
Test level:
P = 100% production test
C = Characterized only
PARAMETER
DC Characteristics
Supply current
Clamp voltage at FILTIN
Discharge current at FILTIN
Discharge current at FILTIN
Clamp charge current at FILTIN
Clamp voltage at FVIDIN
Discharge current at FVIDIN
Discharge current at FVIDIN
Clamp charge current at FVIDIN
R
SET
voltage, pin 12
R
FILT
voltage, pin 1
RNOSIG current, pin 2
Logic output low voltage, V
OL
CONDITIONS
TEST
MIN
TYP
MAX UNIT
P
Pin 4 unloaded
Pin 4, Vin = 2V pk-pk
Pin 4, no signal
Pin 4, Vin = 1V pk-pk
Pin 8 unloaded
Pin 8, Vin = 2V pk-pk
Pin 8, no signal
Pin 8, Vin = 1V pk-pk
P
C
C
P
P
C
C
P
P
P
P
I
OL
= 1.6mA
P
2
1.2
4.5
1.35
1
6.5
1.5
mA
V
A
3
2
1.2
6
3
1.35
1
12
4
1.5
A
mA
V
3
2
1.5
0.35
1.5
6
3
1.75
0.5
2.5
0.35
12
4
2
0.65
3.5
0.8
mA
V
V
A
V
ISSUE 3 - NOVEMBER 2003
SEMICONDUCTORS
2
ZXFV4583
ELECTRICAL CHARACTERISTICS (Cont.)
V
CC
= 5V, R
SET
= 681k , R
FILT
= 22k , R
NOSIG
= 82k , T
amb
= 25 C unless otherwise stated.
PARAMETER
AC Characteristics
FILTIN function input voltage range
Filter voltage gain
Filter attenuation
Slice level
CSYNC prop. Delay, t
CS
VSYNC delay
VSYNC pulse width, t
VSYNC
(PAL)
VSYNC pulse width, t
VSYNC
(NTSC)
VSYNC default delay, t
VSD
HSYNC delay
HSYNC pulse width, t
HSYNC
BKPCH delay, t
BD
BKPCH pulse width, t
B
Relative to pin 4 input
PAL/NTSC
FILTIN to FILOUT
4.4MHz for PAL,
3.6MHz for NTSC
Vin = 1V pk-pk
Relative to pin 4 input
P
P
P
P
P
P
C
C
C
P
P
P
P
P
2.7
3.8
30
0.5
4.9
15
10
40
5.7
19
14
50
250
250
165
195
36
250
5
250
3.7
6.2
400
4.7
45
60
400
2
6.5
V pk-pk
dB
dB
dB
%
ns
ns
s
s
s
ns
s
ns
s
CONDITIONS
TEST MIN TYP MAX
UNIT
Note:
In order to avoid coupling between high speed logic output signals and analog inputs, the test circuit
layout uses connections from the logic output pins routed away from the analog pins. In the application,
similar care in the layout is required, keeping resistors R
FILT
, R
NOSIG
and R
SET
close to their respective
pins, in particular routing signal CSYNC away from pins 1, 2 and 12.
ISSUE 3 - NOVEMBER 2003
3
SEMICONDUCTORS
ZXFV4583
CONNECTIONS
PIN No.
1
PIN NAME
R
FILT
TYPE
Resistor
control
FUNCTION
Controls the input color carrier filter characteristic. An external
resistor R
FILT
connected from this pin to 0V sets the bandwidth.
Smaller R
FILT
gives increased bandwidth. See the detailed operating
description below.
Controls the no-signal detector level. An external resistor R
NOSIG
connected from this pin to 0V sets the threshold voltage level,
according to the equation
V
PMIN
= 0.75 R
NOSIG
/ R
SET
where V
PMIN
is the minimum detected sync pulse amplitude at pin 4
and R
SET
is the resistor value at pin 12.
Composite sync logic output. Includes all sync pulses derived from
the input video.
2
R
NOSIG
Resistor
control
3
CSYNC
Logic out
4
FILTIN
Input to color carrier filter. This is the main analog (unfiltered)
composite video input used when color carrier filtering is required. A
Analog in voltage clamp circuit and adaptive current source are also included
at this node. See the detailed operating description. When the filter
is not used, this pin must be left open circuit.
Logic out
Ground
Vertical sync output. This is an active low pulse commencing on the
first vertical sync pulse trailing (rising) edge and ending near the
second next equalizing pulse. See timing diagram.
Provides ground return path for internal logic output buffer circuits.
Normally connected externally to a common PCB ground plane.
5
6
7
VSYNC
OVD
FILTOUT
Analog out Analog output signal from color carrier filter. The filter voltage gain
is nominally 2. This output is normally capacitor-coupled to pin 8.
Input for filtered analog video signal input. This is the direct input
to the sample/hold and sync slicing comparator providing the logic
Analog in timing edges. This input is normally coupled via an external
capacitor from FILTOUT, pin 7. It may be used as the signal input
where the color carrier filter is not required. Includes a clamp
similar that of pin 4.
Analog out Analog output, a positive voltage typically equal to twice the
(negative) peak sync pulse amplitude if the filter is used.
Logic out
Logic output, which goes high after a time-out delay when no signal
is present. The threshold level is controlled at pin 2.
Burst or Back Porch logic output, an active low monostable pulse
triggered from rising composite sync pulse edges. The width is set
by R
SET
to overlap most of the steady part of the back porch,
assuming the color carrier burst has been attenuated sufficiently by
filtering. This pulse is then suitable for controlling an external black
level clamping circuit. See the timing diagram.
Controls the timing interval of the sample/hold circuit and the
monostable interval for the sync outputs according to the
application. An external resistor, R
SET
connected from this pin to 0V
establishes the timing parameter, to which these times are scaled
together. See the detailed operating description.
Odd field logic output. High during an odd numbered field, low
during even. This output is timed with the start of the VSYNC pulse.
Power supply input, +5V.
Horizontal sync logic output. Monostable output derived from
CSYNC falling edges, it achieves a steady stream of 5µs pulses. The
half line events during the field blanking interval are eliminated. See
timing diagram.
8
FVIDIN
9
10
VLEV
NOSIG
11
BKPCH
Logic out
12
R
SET
Resistor
control
13
14
15
ODDFLD
V+
HSYNC
Logic out
Power in
Logic out
ISSUE 3 - NOVEMBER 2003
SEMICONDUCTORS
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ZXFV4583
DETAILED DESCRIPTION
Introduction
This device includes all the functions required to separate
out the critical timing points of most types of video signal.
A sample-and-hold process is used to establish
accurately the 50% point of the sync pulse. The input is
also filtered to avoid the effect of the color carrier. The
filter is coupled externally. The following paragraphs
give a simplified description of the signal processing.
The vertical sync output
VSYNC
is derived from the
Field pulse group. Where there are short equalization
pulses in the standard systems, these short pulses are
ignored. Essentially, a pulse width discriminator
circuit senses the first of the Field pulses, as they are
wider than those of the rest of the sequence. The
trailing edge of the first negative-going Frame Pulse
(i.e. the rising edge of the first “serration” pulse)
triggers the VSYNC output. In systems with a frame
interval with no serration pulses, a vertical sync output
is provided after a default delay as in
Figure 4.
Also
provided is an
ODDFLD
logic output, which is high
during an odd-numbered field and low during an even
one.
The horizontal sync
HSYNC
is a monostable output
derived from the leading (falling) edge of the
composite sync. The pulse width is about 5 µs. Also,
during the Field blanking sequence, the additional
half-line pulses are removed by a timing circuit with a
pulse interval discrimination function controlled by
R
SET
. R
SET
is normally set to 681k for standard PAL or
NTSC timings. Consequently the scan rate is inversely
proportional to R
SET
.
The Back Porch monostable output
BKPCH
is initiated
from the trailing edge of the composite sync. The pulse
is active low and the width is set according to R
SET
.
Color carrier filter
This low-pass filter provides adjustable attenuation of
the color carrier with low distortion of the remaining
sync pulses so as to ensure accurate timing of the
extracted logic outputs. The control is via an external
resistor R
FILT
connected from pin 1 to ground.
R
FILT
=22k gives corner frequency of
∼1.3MHz
co r re s p ond i n g to ~ 1 2 dB a t t e nu a t io n @
3.58MHz.(Corner freq. Proportional to 1/R
FILT
,
minimum value 18k ). A graph shows how the
bandwidth varies with the resistor value.
Clamping circuits
Clamping circuits are use to limit the signal swing
excursion after AC coupling at both the input to the
filter, FILTIN and the timing extractor input, FVIDIN. In
each case, the sync tip level is maintained at a value of
nominally 1.35V.
Sync timing extraction circuits
The waveforms are depicted in Timing Diagrams,
Figure 1
for PAL (625 lines) and
Figure 2
for NTSC (525
lines). Sample-and-hold circuits are used to obtain
time-delayed voltage values of the sync tip and the
back porch. The sample gates are controlled by a
comparator sensing the video input relative to a
threshold at a fixed offset above the sync tip clamp
level. The sampled voltages are combined in a
potential divider to derive the mean voltage (50%
amplitude), which is used as the sync pulse threshold.
A second comparator then provides
CSYNC,
the logic
version of the composite sync signal. This is delayed
slightly as shown in
Figure 3.
The time delay
comprises that of the input filter and also the smaller
delay of the comparator and logic. The timing of the
sample hold and other time parameters are all
controlled together in unison by the external resistor
R
SET
. A 1% resistor tolerance is recommended. The
sync tip voltage level from the sample-and-hold is
buffered and provided as an analog output,
VLEV.
Loss-of-Signal detector
Loss of signal is indicated by a logic high level at the
output
NOSIG.
The decision threshold is set by an
external resistor R
NOSIG
connected from pin 2 to
ground. R
NOSIG
=100k gives a shut off threshold of
∼250mV
of sync amplitude at FVIDIN or ~130mV on
FILTIN (Threshold proportional to R
NOSIG
, minimum
value 82k ) The table of connections above gives the
equation used to determine a suitable resistor value. A
waiting time of nominally 600 µs occurs before the loss
of signal is flagged.
ISSUE 3 - NOVEMBER 2003
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SEMICONDUCTORS
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