PT7V4050TATCA35.328/19.440 datasheet, PDF

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PT7V4050TATCA35.328/19.440: DescriptionPLL/Frequency Synthesis Circuit,; CategoryAnalog mixed-signal IC The signal circuit; File Size156KB，7 Pages; ManufacturerDiodes Incorporated

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PT7V4050TATCA35.328/19.440 Overview

PLL/Frequency Synthesis Circuit,

PT7V4050TATCA35.328/19.440 Parametric

Parameter Name	Attribute value
Objectid	4000504888
package instruction	DIP,
Reach Compliance Code	compliant
Other features	SEATED HEIGHT CALCULATED
Analog Integrated Circuits - Other Types	PHASE DETECTOR
JESD-30 code	R-PDIP-T16
length	20.32 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

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Features

•

PLL with quartz stabilized VCXO

•

Loss of signals alarm

•

Return to nominal clock upon LOS

•

Input data rates from 8 kb/s to 65 Mb/s

•

Tri-state output

•

User defined PLL loop response

•

NRZ data compatible

•

Single +5.0V power supply

Description

The device is composed of a phase-lock loop with an

integrated VCXO for use in clock recovery, data re-

timing, frequency translation and clock smoothing

applications in telecom and datacom systems.

Crystal Frequencies Supported: 12.000~50.000 MHz.

Block Diagram

CLKIN

DATAIN

HIZ

Phase Detector &

Loss Of Signal

Circuit

RCLK

RDATA

LOS

PHO

LOSIN

CLK1

VCXO

Divider

CLK2

OPN

Amp

OPOUT

OPP

Ordering Information

PT7V4050

Device Type

16-pin clock recoverymodule

PackageLeads

T: Thru-Hole

G: Surface Mount

CLK2 Divider

A: Divide by 2 E: Divide by 32

B: Divide by 4 F: Divide by 64

C: Divide by 8 G: Divide by 128

D: Divide by 16 H: Divide by 256

K: Disable

49.408 / 12.352

CLK2 Frequency

CLK1 Frequency

A: 5.0V supply voltage

B: 3.3V supply voltage

20ppm

32ppm

50ppm

100ppm

Temperature Range

C: 0

C to 70

T: -40

C to 85

12.000

16.128

18.432

22.579

28.000

34.368

44.736

Frequencies using at CLK1 (MHz)

12.288

12.624

13.00

16.384

16.777

16.896

18.936

20.000

20.480

24.576

24.704

25.000

30.720

32.000

32.768

38.880

40.000

41.2416

47.457

49.152

49.408

19.440

35.328

16.000

17.920

22.1184

27.000

33.330

41.943

50.000

40.960

Note:

CLK1 up to 40.960MHz for both 5V and

3.3V for temperature -40oC to 85 oC; CLK1 up to

50MHz for both 5V and 3.3V for temperature 0oC to 70oC.

PT0125(02/06)

Ver:2

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