74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 2 — 10 April 2013
Product data sheet
1. General description
The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC595-Q100; 74HCT595-Q100 are 8-stage serial shift registers with a storage
register and 3-state outputs. The registers have separate clocks. Data is shifted on the
positive-going transitions of the shift register clock input (SHCP). The data in each register
is transferred to the storage register on a positive-going transition of the storage register
clock input (STCP). If both clocks are connected together, the shift register is always one
clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Applications
Serial-to-parallel data conversion
Remote control holding register
NXP Semiconductors
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC595D-Q100
74HCT595D-Q100
74HC595DB-Q100
74HCT595DB-Q100
74HC595PW-Q100
74HCT595PW-Q100
74HC595BQ-Q100
74HCT595BQ-Q100
40 C
to +125
C
DHVQFN16
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
SOT763-1
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
9
8-BIT STORAGE REGISTER
13 OE
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1
2
3
4
5
6
7
mna554
Fig 1.
Functional diagram
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 April 2013
2 of 23
NXP Semiconductors
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
13
12
11
12
10
9
15
1
2
3
4
5
6
7
14
1D
11
R
C1/
SRG8
SHCP STCP
Q7S
Q0
Q1
Q2
14
DS
Q3
Q4
Q5
Q6
Q7
MR
10
OE
13
mna552
EN3
C2
2D
3
15
1
2
3
4
5
6
7
9
mna553
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
STAGE 0
DS
D
FF0
CP
SHCP
R
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
FF7
CP
R
Q
Q7S
MR
D
Q
D
Q
LATCH
CP
STCP
OE
LATCH
CP
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 4.
Logic diagram
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 April 2013
3 of 23
NXP Semiconductors
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6. Pinning information
6.1 Pinning
+& 4
+&7 4
4
4
4
4
4
4
4
*1'
DDD
9
&&
4
'6
2(
67&3
6+&3
05
46
+& 4
+&7 4
4
4
4
4
4
4
4
*1'
DDD
9
&&
4
'6
2(
67&3
6+&3
05
46
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration (T)SSOP16
+& 4
+&7 4
WHUPLQDO
LQGH[ DUHD
4
4
4
4
4
4
*1'
46
*1'
9
&&
4
'6
2(
67&3
6+&3
05
4
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to
GND.
Fig 7.
Pin configuration for DHVQFN16
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 April 2013
4 of 23
NXP Semiconductors
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6.2 Pin description
Table 2.
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
V
CC
Pin description
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
supply voltage
7. Functional description
Table 3.
Control
SHCP STCP OE
X
X
X
X
X
X
L
L
H
L
MR
L
L
L
H
Function table
[1]
Input
DS
X
X
X
H
Output
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Function
X
L
L
H
H
X
X
NC
Q6S
QnS
QnS
[1]
H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 April 2013
5 of 23
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