82P33724 datasheet, PDF - EEWORLD Datasheet

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82P33724: DescriptionDifferential reference inputs; File Size215KB，14 Pages; ManufacturerICS ( IDT ); Websitehttp://www.icst.com

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82P33724 Overview

Differential reference inputs

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Port Synchronizer for IEEE 1588 and

Synchronous Ethernet

HIGHLIGHTS

•

82P33724

SHORT FORM DATA SHEET

DPLL1 and DPLL2 can be used on line cards to manage the genera-

tion of synchronous port clocks and IEEE 1588 synchronization sig-

nals based on multiple system backplane references

DPLL3 can be used on line cards to select incoming line clocks for

use on system backplanes; it can also be used for general purpose

timing applications

APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to

20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate

IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals

Fractional-N input dividers support a wide range of reference fre-

quencies

The device can be configured from an external EEPROM after reset

Differential reference inputs (IN1 to IN4) accept clock frequencies

between 2 kHz and 650 MHz

Single ended inputs (IN5 to IN6) accept reference clock frequencies

between 2 kHz and 162.5 MHz

Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any

clock reference input

Reference monitors qualify/disqualify references depending on activ-

ity, frequency and LOS pins

Automatic reference selection state machines select the active refer-

ence for each DPLL based on the reference monitors, priority tables,

revertive and non-revertive settings and other programmable settings

Fractional-N input dividers enable the DPLLs to lock to a wide range

of reference clock frequencies including: 10/100/1000 Ethernet, 10G

Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS frequen-

cies

Any reference inputs (IN1 to IN6) can be designated as external sync

pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-

able reference clock input

FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses

that are aligned with the selected external input sync pulse input and

frequency locked to the associated reference clock input

DPLL1 and DPLL2 can be configured with bandwidths between 18

Hz and 567 Hz

DPLL1 and DPLL2 lock to input references with frequencies between

2 kHz and 650 MHz

DPLL3 locks to input references with frequencies between 8 kHz and

650 MHz

DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/

OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks

are directly available on OUT1 and OUT8

FEATURES

•

DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on

OUT9 and OUT10

APLL1 and APLL2 can be connected to DPLL1 and DPLL2

APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or

SONET/SDH frequencies

Any of eight common TCXO/OCXO frequencies can be used for the

System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,

24.576 MHz, 25 MHz or 30.72 MHz

The I2C slave, SPI or the UART interface can be used by a host pro-

cessor to access the control and status registers

The I2C master interface can automatically load a device configura-

tion from an external EEPROM after reset

Differential outputs OUT3 to OUT6 output clocks with frequencies

between 1 PPS and 650 MHz

Single ended outputs OUT1, OUT2, OUT7, and OUT8 output clocks

with frequencies between 1 PPS and 125 MHz

Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi-

ples up to 100 MHz

DPLL1 and DPLL2 support independent programmable delays for

each of IN1 to IN16; the delay for each input is programmable in

steps of 0.61 ns with a range of ~±78 ns

The input to output phase delay of DPLL1 and DPLL2 is programma-

ble in steps of 0.0745 ps with a total range of ±20

μs

The clock phase of each of the output dividers for OUT1 to OUT8 is

individually programmable in steps of ~200 ps with a total range of +/

-180°

1149.1 JTAG Boundary Scan

72-pin QFN green package

Synchronous clock generation for 10/40G and lower rate, Ethernet,

PON OLT and SONET/SDH line card

Access routers, edge routers, core routers

Carrier Ethernet switches

Multiservice access platforms

PON OLT

LTE eNodeB

APPLICATIONS

•

82P33724 REVISION 1 09/23/14

82P33724 SHORT FORM DATA SHEET

DESCRIPTION

The 82P33724 Port Synchronizer for IEEE 1588 and Synchronous Ethernet provides tools to manage timing references, clock conversion and tim-

ing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock genera-

tion; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize Ethernet

interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

The 82P33724 accepts four differential reference inputs and two single ended reference inputs that can operate at common Ethernet, SONET/

SDH and PDH frequencies that range from 2 kHz to 650 MHz. The references are continually monitored for loss of signal and for frequency offset per

user programmed thresholds. All of the references are available to all three Digital PLLs (DPLLs). The active reference for each DPLL is determined

by forced selection or by automatic selection based on user programmed priorities, locking allowances, reference monitors, and LOS inputs.

The 82P33724 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1/DPLL2 can lock to the clock reference

and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference

inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals

can have a frequency of 1 PPS, 2 kHz, 4kHz or 8 kHz. This feature enables DPLL1/DPLL2 to phase align its frame sync and multi-frame sync outputs

with a sync input without the need use a low bandwidth setting to lock directly to the sync input.

The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on

the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre-

quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data

acquired while in Locked mode to generate accurate frequencies when input references are not available.

The 82P33724 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-

mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the

DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.

DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 18 Hz to 567 Hz. DPLL3 is a wideband (BW > 25Hz) fre-

quency translator that can be used, for example, to convert a recovered SyncE clock to a 25MHz backplane clock.

Clocks generated by DPLL1 and DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The

output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces, and for IEEE 1588 time stamps clocks and 1 PPS

signals.

All 82P33724 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the

DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.

PORT SYNCHRONIZER FOR IEEE 1588 AND

SYNCHRONOUS ETHERNET

REVISION 1 09/23/14

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