FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
3.3 Volt Synchronous x36 First-In / First-Out Queue
FlexQ
TM
III
Document Title
3.3 Volt Synchronous x36 First-In / First-Out Queue
Revision History
Rev. No.
C
D
History
pg. 1,2, 6, 9, 10, 11, 12, 13, 14, 16, 27, 28, 30, 31, 39
Add Pb-Free package type
Issue Date
January 10, 2002
December 20, 2006
Remark
(December, 2006, Version D)
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
3.3 Volt Synchronous x36 First-In / First-Out Queue
FlexQ
TM
III
3.3 Volt Synchronous x36 First-In/First-Out Queue
Memory Organization
131,072 x 36
65,536 x 36
32,768 x 36
16,384 x 36
Device
FQV36110
FQV36100
FQV3690
FQV3680
Memory Organization
8,192 x 36
4,096 x 36
2,048 x 36
1,024 x 36
Device
FQV3670
FQV3660
FQV3650
FQV3640
Key Features
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Industry leading First-In/First-Out Queues (up to 166MHz)
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
User selectable input and output ports bus-sizing
Big Endian/Little Endian user selectable byte representation
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
Master Reset clears all previously programmed configurations including Write and Read pointers
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
First Word Fall Through (FWFT) and Standard Timing modes
Presets for eight different Almost Full and Almost Empty offset values
Parallel/Serial programming of
PRAF and PRAE offset values
Programmable 8-bit or 9-bit parallel programming mode for offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
PRAF and PRAE operate in either synchronous or asynchronous mode
Asynchronous output enable tri-state data output drivers
Data retransmission with programmable zero or normal latency mode
Available package: 128 - pin Plastic Thin Quad Flat Pack (TQFP)
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
AMIC’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 6.0 Gbps), with a wide range of memory configurations (from
1,024 x 36 to 131,072 x 36). System designer has full flexibility of implementing deeper and wider queues using FWFT mode and width
expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between transmitters and receivers. User programmable
Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output
Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability.
Master Reset clears all previously programmed configurations by providing a low pulse on
MRST
pin. In addition, Write and Read pointers
to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read
pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high transition of
RCLK. Subsequent reads from the queue will require asserting
REN
. This feature is useful when implementing depth expansion functions.
In this mode,
DRDY
and QRDY are used instead of
FULL
and EMPTY respectively.
In Standard mode, always assert
REN
for read operation.
FULL
and EMPTY are used instead of DRDY and QRDY respectively.
(December, 2006, Version D)
1
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQ
TM
III
Product Description (Continued)
Bus matching feature is available with the following memory configurations:
Input Bus Width
x9
x18
x36
x36
x36
Output Bus Width
x36
x36
x36
x18
x9
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full (
PRAF
) and Almost Empty (
PRAE
) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit parallel
programming modes for offset values can be selected for convenience.
PRAF
,
PRAE
, and
HALF
are available in either FWFT or Standard mode.
PRAF
and
PRAE
can operate in either synchronous or
asynchronous mode.
At any time, data previously read from the queue can be retransmitted by asserting
RET
pin at the low to high transition of RCLK for a
retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0
th
(Read
pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit operation.
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 128
- pin Plastic TQFP is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network
switching, etc.
(December, 2006, Version D)
2
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQ
TM
III
Block Diagram of Single Synchronous Queue
131,072 x 36 / 65,536 x 36 / 32,768 x 36 / 16,384 x 36 / 8,192 x 36 / 4,096 x 36 / 2,048 x 36 / 1,024 x 36
PARTIAL RESET (PRST )
MASTER RESET (MRST )
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD ( LOAD)
x36, x18, x9 DATA IN (D
35 - 0
)
SERIAL DATA ENABLE (SDEN)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
( FULL / DRDY)
PROGRAMMABLE
ALMOST-FULL (PRAF )
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
READ ENABLE (REN )
OUTPUT ENABLE (OE)
x36, x18, x9 DATA OUT (Q
35 - 0
)
RETRANSMIT (
RET
)
EMPTY FLAG / OUTPUT READY
( EMPTY/
QRDY
)
PROGRAMMABLE ALMOST-
EMPTY ( PRAE )
HALF-FULL FLAG ( HALF )
BIG-ENDIAN / LITTLE-ENDIAN (ES)
INTERSPERSED/NON-INTERSPERSED
PARITY (IPAR)
BUS
MATCHING 2
(BM2)
BUS
MATCHING 1
(BM1)
BUS
MATCHING 0
(BM0)
Figure 1. Single Device Configuration Signal Flow Diagram
(December, 2006, Version D)
3
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQ
TM
III
WCLK
IPAR
LOAD SDEN FWFT/SDI
WEN
Write Control
Logic
FULL /
DRDY
PRAF
EMPTY / QRDY
PRAE
Flag Logic
Offset Register
Write Pointer
HALF
FWFT/SDI
SFM
PFS1
PFS0
D
35-0
x36, x18, x9
Input Register
SRAM
Output Register
Output
Buffer
Q
35-0
x36, x18, x9
OE
Read Pointer
Read Control
Logic
Reset
Bus
Configuration
RETZL RET
RCLK REN
MRST PRST
ES
BM2 BM1 BM0
Figure 2. Device Architecture
(December, 2006, Version D)
4
AMIC Technology, Corp.
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