MMFT3055E
Power MOSFET
1.7 Amp, 60 Volts
N−Channel TMOS E−FETt SOT−223
This advanced E−FET is a TMOS Medium Power MOSFET
designed to withstand high energy in the avalanche and commutation
modes. This new energy efficient device also offers a drain−to−source
diode with a fast recovery time. Designed for low voltage, high speed
switching applications in power supplies, dc−dc converters and PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients. The device is housed in the SOT−223 package which is
designed for medium power surface mount applications.
Features
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V
DSS
60 V
R
DS(ON)
TYP
150 mΩ
N−Channel
2,4
D
I
D
MAX
1.7 A
•
Silicon Gate for Fast Switching Speeds
•
Low R
DS(on)
— 0.15
Ω
max
•
The SOT−223 Package can be Soldered Using Wave or Reflow. The
1
G
S
3
4
1
Formed Leads Absorb Thermal Stress During Soldering, Eliminating
the Possibility of Damage to the Die
•
Available in 12 mm Tape and Reel
Use MMFT3055ET1 to order the 7 inch/1000 unit reel.
Use MMFT3055ET3 to order the 13 inch/4000 unit reel.
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage− Continuous
Drain Current
−
Continuous
Drain Current
−
Single Pulse (t
p
≤
10
ms)
Total Power Dissipation @ T
A
= 25°C
Derate above 25°C (Note 1)
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 60 Vdc, V
GS
= 10 Vdc, Peak
I
L
= 1.7 Apk, L = 0.2 mH, R
G
= 25
Ω
)
Thermal Resistance
−
Junction to Ambient (surface mounted)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
Symbol
V
DSS
V
GS
I
DM
P
D
T
J
, T
stg
E
AS
168
°C/W
°C
I
D
Value
60
±
20
1.7
6.8
0.8
6.3
−65
to
150
Unit
Vdc
Vdc
Adc
Apk
Watts
mW/°C
°C
mJ
MARKING
DIAGRAM
2
3
SOT−223
CASE 318E
STYLE 3
L
WW
= Location Code
= Work Week
3055
LWW
PIN ASSIGNMENT
4
Drain
1
2
3
R
θJA
T
L
156
260
Gate
Drain
Source
ORDERING INFORMATION
Device
MMFT3055ET1
MMFT3055ET3
Package
SOT−223
SOT−223
Shipping
†
1000 Tape & Reel
4000 Tape & Reel
1. Power rating when mounted on FR−4 glass epoxy printed circuit board
using recommended footprint.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 5
1
Publication Order Number:
MMFT3055E/D
MMFT3055E
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage, (V
GS
= 0, I
D
= 250
mA)
Zero Gate Voltage Drain Current, (V
DS
= 60 V, V
GS
= 0 V)
Gate−Body Leakage Current, (V
GS
= 20 V, V
DS
= 0 V)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage, (V
DS
= V
GS
, I
D
= 1.0 mA)
Static Drain−to−Source On−Resistance, (V
GS
= 10 V, I
D
= 0.85 A)
Drain−to−Source On−Voltage, (V
GS
= 10 V, I
D
= 1.7 A)
Forward Transconductance, (V
DS
= 15 V, I
D
= 0.85 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
Forward On−Voltage
Forward Turn−On Time
Reverse Recovery Time
(V
DS
= 48 V, I
D
= 1.7 A,
V
GS
= 10 Vdc)
See Figures 15 and 16
(V
DD
= 25 V, I
D
= 0.85 A
V
GS
= 10 V, R
G
= 50
W,
R
GS
= 25
W)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
V
SD
t
on
t
rr
15
22
31
49
12.5
2.0
4.5
0.8
Limited by stray inductance
50
ns
Vdc
nC
ns
(V
DS
= 20 V,
V
GS
= 0 V, f = 1.0 MHz)
C
iss
C
oss
C
rss
430
225
40
pF
V
GS(th)
R
DS(on)
V
DS(on)
g
FS
2.2
2.0
4.5
0.15
0.34
Vdc
W
Vdc
mhos
V
(BR)DSS
I
DSS
I
GSS
60
10
100
Vdc
mAdc
nAdc
Symbol
Min
Typ
Max
Unit
SOURCE DRAIN DIODE CHARACTERISTICS
(1)
I
S
= 1.7 A, V
GS
= 0 V
I
S
= 1.7 A, V
GS
= 0 V,
dl
S
/dt = 400 A/ms,
V
R
= 30 V
2. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
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2
MMFT3055E
10
8V
10 V
V
GS
= 20 V
V GS(TH), GATE THRESHOLD VOLTAGE
(NORMALIZED)
7V
T
J
= 25°C
6V
1.2
V
DS
= V
GS
I
D
= 1 mA
1.1
1
I D, DRAIN CURRENT (AMPS)
8
6
4
5V
2
4.5 V
4V
0
0
2
4
6
8
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.9
0.8
0.7
−50
0
50
T
J
, JUNCTION TEMP (°C)
100
150
Figure 1. On Region Characteristics
Figure 2. Gate−Threshold Voltage Variation
With Temperature
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.3
V
GS
= 10 V
0.25
0.2
0.15
0.1
0.05
0
10
T
J
= −55°C
I D, DRAIN CURRENT (AMPS)
8
25°C
100°C
V
DS
= 10 V
6
T
J
= 100°C
25°C
−55
°C
4
2
0
0
2
4
6
8
10
0
2
4
I
D
, DRAIN CURRENT (AMPS)
6
8
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. Transfer Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.5
T
J
= 25°C
I
D
= 1.7 A
0.4
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.3
Figure 4. On−Resistance versus Drain Current
V
GS
= 10 V
I
D
= 1.7 A
0.2
0.3
0.2
0.1
0.1
0
3
6
9
12
15
18
21
0
−50
0
50
100
150
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance versus
Gate−to−Source Voltage
Figure 6. On−Resistance versus Junction
Temperature
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3
MMFT3055E
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on an ambient temperature of
25°C and a maximum junction temperature of 150°C.
Limitations for repetitive pulses at various ambient
temperatures can be determined by using the thermal
response curves. Application Note, AN569, “Transient
Thermal Resistance−General Data and Its Use” provides
detailed instructions.
SWITCHING SAFE OPERATING AREA
10
V
GS
= 20 V
SINGLE PULSE
T
A
= 25°C
1
20 ms
100 ms
DC
0.1
1s
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
I D, DRAIN CURRENT (AMPS)
500 ms
100
0.01
0.1
The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
I
DM
and the breakdown voltage, BV
DSS
. The switching
SOA is applicable for both turn−on and turn−off of the
devices for switching times less than one microsecond.
r(t), EFFECTIVE THERMAL RESISTANCE (NORMALIZED)
1.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
(pk)
R
θJA
(t) = r(t) R
θJA
R
θJA
= 156°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
A
= P
(pk)
R
θJA
(t)
0.01
0.01
SINGLE PULSE
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 8. Thermal Response
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
10 defines the limits of safe operation for commutated
source−drain current versus re−applied drain voltage when
the source−drain diode has undergone forward bias. The
curve shows the limitations of I
FM
and peak V
DS
for a given
rate of change of source current. It is applicable when
waveforms similar to those of Figure 9 are present. Full or
half−bridge PWM DC motor controllers are common
applications requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dI
S
/dt is specified with a maximum value.
Higher values of dI
S
/dt require an appropriate derating of
I
FM
, peak V
DS
or both. Ultimately dI
S
/dt is limited primarily
by device, package, and circuit impedances. Maximum
device stress occurs during t
rr
as the diode goes from
conduction to reverse blocking.
V
DS(pk)
is the peak drain−to−source voltage that the
device must sustain during commutation; I
FM
is the
maximum forward source−drain diode current just prior to
the onset of commutation.
V
R
is specified at 80% rated BV
DSS
to ensure that the
CSOA stress is maximized as I
S
decays from I
RM
to zero.
R
GS
should be minimized during commutation. T
J
has
only a second order effect on CSOA.
Stray inductances in ON Semiconductor’s test circuit are
assumed to be practical minimums. dV
DS
/dt in excess of
10 V/ns was attained with dI
S
/dt of 400 A/ms.
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4
MMFT3055E
15 V
V
GS
0
I
FM
90%
I
S
10%
t
on
I
RM
t
frr
V
DS(pk)
V
R
V
DS
0.25 I
RM
dl
S
/dt
t
rr
V
f
V
dsL
MAX. CSOA
STRESS AREA
Figure 9. Commutating Waveforms
10
9
IS , SOURCE CURRENT (AMPS)
8
7
6
5
4
3
2
1
0
0
10
20
30
40
50
60
70
80
90
100
V
GS
+
dI
S
/dt
≤
400 A/μs
−
V
R
I
FM
+
20 V
−
R
GS
DUT
I
S
V
DS
L
i
V
R
= 80% OF RATED V
DSS
V
dsL
= V
f
+ L
i
⋅
dl
S
/dt
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 10. Commutating Safe Operating
Area (CSOA)
Figure 11. Commutating Safe Operating Area
Test Circuit
BV
DSS
L
V
DS
I
L
V
DD
t
R
G
V
DD
t
P
t, (TIME)
I
L(t)
Figure 12. Unclamped Inductive Switching
Test Circuit
Figure 13. Unclamped Inductive Switching
Waveforms
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