MTD20P03HDL
Preferred Device
Power MOSFET
20 Amps, 30 Volts, Logic Level
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. This energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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V
(BR)DSS
30 V
R
DS(on)
TYP
90 mW@5.0 V
I
D
MAX
20 A
(Note 1)
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
P−Channel
D
w
G
S
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
4
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
1
3
DPAK
CASE 369D
Style 2
2
1 2
MARKING DIAGRAMS
4
Drain
YWW
20P
03HL
2
1
3
Drain
Gate
Source
4
Drain
YWW
20P
03HL
1 2 3
Gate Drain Source
Package
DPAK
DPAK
Straight Lead
DPAK
Shipping
75 Units/Rail
75 Units/Rail
2500 Tape & Reel
Publication Order Number:
MTD20P03HDL/D
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−Source Voltage
−
Continuous
−
Non−Repetitive (t
p
v10
ms)
Drain Current
−
Continuous
−
Continuous @ 100°C
−
Single Pulse (t
p
v10
μs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
C
= 25°C
(Note 2)
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc,
I
L
= 19 Apk, L = 1.1 mH, R
G
= 25
Ω)
Thermal Resistance
−
Junction−to−Case
−
Junction−to−Ambient (Note 1)
−
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
30
30
"15
"20
19
12
57
75
0.6
1.75
−55
to
150
200
3
DPAK
CASE 369C
Style 2
4
I
DM
P
D
T
J
, T
stg
E
AS
°C
mJ
20P03HL Device Code
Y
= Year
WW
= Work Week
R
θJC
R
θJA
R
θJA
T
L
1.67
100
71.4
260
°C/W
ORDERING INFORMATION
Device
MTD20P03HDL
°C
MTD20P03HDL−1
MTD20P03HDLT4
1. When surface mounted to an FR−4 board using the minimum
recommended pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
March 2006
−
Rev. 6
1
MTD20P03HDL
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±15
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 4.0 Vdc, I
D
= 10 Adc)
(V
GS
= 5.0 Vdc, I
D
= 9.5 Adc)
Drain−to−Source On−Voltage (V
GS
= 5.0 Vdc)
(I
D
= 19 Adc)
(I
D
= 9.5 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 8.0 Vdc, I
D
= 9.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DD
= 15 Vdc, I
D
= 19 Adc,
V
GS
= 5.0 Vdc,
R
G
= 1.3
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
(V
DS
= 24 Vdc, I
D
=19 Adc,
V
GS
= 5.0 Vdc)
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(C
pk
≥
2.0) (Note 5)
Reverse Recovery Time
(See Figure 15)
(I
S
= 19 Adc, V
GS
= 0 Vdc)
(I
S
= 19 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
Vdc
−
−
−
−
−
−
3.1
2.56
78
50
28
0.209
3.4
−
−
−
−
−
μC
nH
−
−
4.5
7.5
−
nH
−
ns
−
−
−
−
−
−
−
−
18
178
21
72
15
3.0
11
8.2
25.2
246.4
26.6
98
22.4
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
770
360
130
1064
504
182
pF
(C
pk
≥
2.0) (Note 5)
V
GS(th)
Vdc
1.0
−
−
1.5
4.0
120
90
0.94
−
6.0
2.0
−
−
99
Vdc
−
−
5.0
2.2
1.9
−
mhos
mV/°C
mΩ
(C
pk
≥
2.0) (Note 5)
V
(BR)DSS
Vdc
30
−
−
−
−
−
15
−
−
−
−
−
10
100
100
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
(C
pk
≥
2.0) (Note 5)
R
DS(on)
V
DS(on)
g
FS
t
rr
(I
S
= 19 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
t
a
t
b
Q
RR
L
D
L
S
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
5. Reflects typical values. C
pk
= Absolute Value of Spec (Spec−AVG/3.516
μA).
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2
MTD20P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40
T
J
= 25°C
I D , DRAIN CURRENT (AMPS)
32
V
GS
= 10 V
8V
6V
5V
I D , DRAIN CURRENT (AMPS)
32
4.5 V
24
4V
16
3.5 V
8
0
0
1
2
3
4
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
3V
2.5 V
5
40
V
DS
≥
5 V
T
J
= − 55°C
25°C
100°C
24
16
8
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.16
0.16
Figure 2. Transfer Characteristics
V
GS
= 5 V
T
J
= 25°C
0.14
T
J
= 100°C
0.12
0.14
0.12
V
GS
= 5 V
0.10
25°C
0.10
0.08
0.06
0
4
8
12
16
− 55°C
0.08
10 V
0.06
0
4
8
12
16
20
24
28
32
36
40
I
D
, DRAIN CURRENT (AMPS)
20
24
28
32
36
40
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.3
V
GS
= 5 V
I
D
= 10 A
1.2
I DSS, LEAKAGE (nA)
100
V
GS
= 0 V
T
J
= 125°C
1.1
10
1.0
0.9
0.8
− 50
100°C
− 25
0
25
50
75
100
125
150
1
0
4
8
12
16
20
24
28
32
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
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3
Figure 6. Drain−To−Source Leakage
Current versus Voltage
MTD20P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
2800
V
DS
= 0 V
2400
C, CAPACITANCE (pF)
2000
1600
1200 C
rss
800
400
0
10
5
V
GS
0
V
DS
5
10
C
iss
V
GS
= 0 V
T
J
= 25°C
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
C
iss
C
oss
C
rss
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTD20P03HDL
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
7
6
5
Q1
4
3
2
1
0
0
2
Q3
4
6
8
10
12
I
D
= 19 A
T
J
= 25°C
V
DS
14
QT
Q2
V
GS
20
15
10
5
0
16
35
30
25
1000
V
DD
= 15 V
I
D
= 19 A
V
GS
= 5.0 V
T
J
= 25°C
t, TIME (ns)
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t
r
100
t
f
t
d(off)
t
d(on)
10
1
R
G
, GATE RESISTANCE (OHMS)
10
Q
G
, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
20
I S , SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
16
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
12
8
4
0
0.3
0.7
1.1
1.5
1.9
2.3
2.7
3.1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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5
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