PCS3P2191A
Product Preview
Spread Spectrum Clock
Generator
Description
PCS3P2191A is a versatile spread spectrum frequency modulator
that generates four low EMI 4x clocks at the output. PCS3P2191A
offers seven selectable centre spread options of
±0.5%
to
±2.0%,
and a
no spread option.
(Refer
to
Spread Deviation Selection Table).
PCS3P2191A reduces electromagnetic interference (EMI) at the clock
source, allowing system wide reduction of EMI of all clock dependent
signals. The PCS3P2191A allows significant system cost savings by
reducing the number of circuit board layers, ferrite beads, and
shielding that are traditionally required to pass EMI regulations. The
PCS3P2191A uses the most efficient and optimized modulation
profile approved by the FCC and is implemented in a proprietary all
digital method. The Device is available in 16−Pin TSSOP package, in
Commercial and Industrial temperature range.
Application
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TSSOP−16
T SUFFIX
CASE 948AN
PIN CONFIGURATION
VDD
GND
S2
GND
CLK1
CLK2
GND
XIN / CLKIN
1
VDD
S0
S1
GND
CLK4
CLK3
GND
XOUT
(Top View)
PCS3P2191A is targeted for LCD panel application.
Features
•
•
•
•
•
•
•
•
•
•
Generates Four 4x Low EMI Spread Spectrum Clocks
Input Frequency: 10 MHz
−
25 MHz
Output Frequency: 40 MHz
−
100 MHz
Internal Loop Filter Minimizes External Components and Board
Space
Selectable Centre Spread Frequency Deviation:
±0.5%, ±0.75%, ±1.0%, ±1.25%, ±1.5%, ±1.75%, ±2.0%
Supply Voltage: 3.3 V
±
0.3 V
Commercial and Industrial Temperature Range
16−pin TSSOP Package
Advanced Low Power CMOS Process
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. P2
1
Publication Order Number:
PCS3P2191A/D
PCS3P2191A
S2
S1
S0
VDD
2
PLL
Modulation
CLKIN / XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
VCO
Output
Divider
CLK[1:4]
4
5
GND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
V
DD
GND
S2
GND
CLK1
CLK2
GND
XIN / CLKIN
XOUT
GND
CLK3
CLK4
GND
S1
S0
V
DD
Type
P
P
I
P
O
O
P
I
O
P
O
O
P
I
I
P
Description
Power Supply Voltage Pin. Connect to +3.3 V.
Ground Connection. Connect to system ground.
Spread range select. Digital logic input used to select frequency deviation
(Refer to
Spread Deviation Table).
This pin has an internal pull−up resistor.
Ground Connection. Connect to system ground.
Low EMI 4x clock output.
Low EMI 4x clock output.
Ground Connection. Connect to system ground.
Crystal connection or external reference clock input.
Crystal connection. If using an external reference, this pin must be left unconnected.
Ground Connection. Connect to system ground.
Low EMI 4x clock output.
Low EMI 4x clock output.
Ground Connection. Connect to system ground.
Spread range select. Digital logic input used to select frequency deviation
(Refer to
Spread Deviation Table).
This pin has an internal pull−up resistor.
Spread range select. Digital logic input used to select frequency deviation
(Refer to
Spread Deviation Table).
This pin has an internal pull−up resistor.
Power Supply Voltage Pin. Connect to +3.3 V.
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2
PCS3P2191A
Table 2. SPREAD DEVIATION SELECTION
(For an Input CLK = 15 MHz.)
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Deviation (+%)
OFF
0.5
0.75
1.0
1.25
1.5
1.75
2.0
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
IN
V
OUT
T
STG
T
s
T
J
T
DV
Parameter
Supply Voltage pin with respect to Ground
Input Voltage pin with respect to Ground
Output Voltage pin with respect to Ground
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
VSS−0.5 to VDD+0.5
VSS−0.5 to VDD+0.5
−55
to +125
260
150
2
Unit
V
V
V
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
V
DD
T
A
C
L
C
IN
Operating Voltage
Operating Temperature
Load Capacitance
Input Capacitance
5
Description
Min
3.0
−40
Typ
3.3
Max
3.6
+85
15
Unit
V
°C
pF
pF
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3
PCS3P2191A
Table 5. DC ELECTRICAL CHARACTERISTICS
(TA =
−40°C
to +85°C, VDD = 3.3 V
±
0.3 V)
Symbol
V
IL
V
IH
I
IL
I
IH
I
IL
I
IH
V
OL
V
OH
I
CC
I
DD
V
DD
t
ON
Z
OUT
C
IN
C
L
Input low voltage
Input high voltage
Input low current
Input high current
Input low current
Input high current
Output low voltage
Output high voltage
Dynamic supply current (Unloaded Outputs)
Static supply current standby mode (Note 1)
Operating voltage
Power up time (first locked clock cycle after power up) (Note 2)
Clock output impedance
Input Capacitance
Load Capacitance
27
5
15
3.0
3.3
I
OL
= 12 mA
I
OH
=
−12
mA
VSS
2.4
8
15
(S0:S1:S2)
(XIN / CLKIN)
Parameter
Min
VSS−0.3
2.0
Typ
Max
0.8
VDD+0.3
−35
+35
−50
+50
0.4
V
DD
26
8
3.6
5
V
V
mA
mA
V
mS
W
pF
pF
mA
Unit
V
V
mA
1. CLKIN pulled Low.
2. V
DD
and CLKIN inputs are stable.
Table 6. AC ELECTRICAL CHARACTERISTICS
(TA =
−40°C
to +85°C, VDD = 3.3 V
±
0.3 V)
Symbol
XIN / CLKIN
CLKOUT
F
MOD
t
LH
(Note 3)
t
HL
(Note 3)
t
JC
(Note 3)
t
JP
(Note 3)
t
D
(Note 3)
Input Clock frequency
Output Clock frequency
Spread Spectrum Modulation Rate
Output rise time (Measured from 20% to 80%)
Output fall time (Measured from 80% to 20%)
Output frequency Synthesis error (With SSOFF)
Cycle−to−Cycle Jitter
Period Jitter (With SSOFF)
Output duty cycle
45
(Pin 5,6,11,12)
Parameter
Min
10
40
26
Typ
15
60
39
1.5
1.0
0
±250
±150
50
±325
±200
55
Max
25
100
65
2
1.5
Unit
MHz
MHz
KHz
nS
nS
ppm
pS
pS
%
3. t
LH
and t
HL
are measured with a capacitive load of 15 pF.
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4
PCS3P2191A
Crystal
R1 = 510
W
C1
C2
Figure 2. Typical Crystal Oscillator Circuit
Table 7. TYPICAL CRYSTAL SPECIFICATIONS
Fundamental AT Cut Parallel Resonant Crystal
Nominal frequency
Frequency tolerance
Operating temperature range
Load capacitance
Shunt capacitance
ESR
15 MHz
±50
ppm or better at 25°C
−45°C
to +90°C
18 pF
7 pF maximum
25
W
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MCU
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