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ZL30101

Description
T1/E1 Stratum 3 System Synchronizer
File Size322KB,34 Pages
ManufacturerZarlink Semiconductor (Microsemi)
Websitehttp://www.zarlink.com/
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ZL30101 Overview

T1/E1 Stratum 3 System Synchronizer

ZL30101
T1/E1 Stratum 3 System Synchronizer
Data Sheet
Features
Supports Telcordia GR-1244-CORE Stratum 3
Supports G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to
any combination of 8 kHz, 1.544 MHz, 2.048 MHz,
8.192 MHz or 16.384 MHz inputs
Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz and either 4.096 MHz &
8.192 MHz or 32.768 MHz & 65.536 MHz
Provides 5 styles of 8 kHz framing pulses
Holdover frequency accuracy of 1 x 10
-8
Lock, Holdover and Out of Range indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Less than 0.6 ns
pp
jitter on all output clocks
External master clock source: clock oscillator or
crystal
Ordering Information
ZL30101QDC
64 pin TQFP
October 2004
-40°C to +85°C
Applications
Synchronization and timing control for multi-trunk
DS1/E1 systems such as DSLAMs, gateways and
PBXs
Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
OSCi OSCo
Master Clock
REF0
REF1
MUX
TIE_CLR
BW_SEL
LOCK
OUT_SEL
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
DS1
Synthesizer
C1.5o
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
REF_FAIL0
REF_FAIL1
Reference
Monitor
TIE
Corrector
Enable
Mode
Control
Feedback
REF_SEL
State Machine
RST
Frequency
Select
MUX
IEEE
1149.1a
TRST
MODE_SEL1:0
HMS
HOLDOVER
TCK TDI
TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.

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