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SI3048

Description
GLOBAL MC 97 SILICON DAA
File Size1MB,64 Pages
ManufacturerETC
Download Datasheet View All

SI3048 Overview

GLOBAL MC 97 SILICON DAA

Si3038
G
L O B A L
M C ’ 9 7 S
I L I C O N
DAA
Features
Complete DAA includes:
AC’97 2.1 Compliant
Primary or Secondary Codec
Global Phone Line Interface
Compliant with FCC, CTR21,
JATE, and Other PTTs
84 dB Dynamic Range TX/RX
Paths
3.3 V or 5 V Power Supply
Greater than 3000 V Isolation
Integrated Ring Detector
Wake-Up On Ring
Caller ID Support
Integrated Analog Front End
2- to 4-Wire Hybrid
Low-Power Standby Mode
Low Profile SOIC Packages
Patented ISOcap™ Technology
Ordering Information:
See page 59.
Applications
Software Modems
Audio/Telephony Sub-Systems
Audio/Modem Riser Cards (AMR)
Mobile Daughter Cards (MDC)
Mini-PCI Cards
Pin Assignments
Si3024 (SOIC)
MCLK/XIN
XOUT
BIT_CLK
V
D
SDA TA _IN
SDA TA _OUT
SY NC
RESET
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GPIO_A
GPIO_B
ID1
V
A
GND
C1A
ID0
A OUT
Description
The Si3038 is an integrated direct access arrangement (DAA) chipset that
provides a digital, programmable line interface to meet global telephone
line requirements. Available in two 16-pin small outline packages (AC’97
interface on Si3024 and phone-line interface on Si3014), the chipset
eliminates the need for an analog front end (AFE), an isolation
transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3038
dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The
Si3024 complies with the AC’97 2.1 specification.
Si3024 (TSSOP)
SDA TA _IN
SDA TA _OUT
SY NC
RESET
A OUT
ID0
C1A
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
D
BIT_CLK
XOUT
MCLK/XIN
GPIO_A
GPIO_B
ID1
V
A
Functional Block Diagram
Si3024
XOUT
MCLK/XIN
RESET
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
AC'97
Digital
Interface
Clock
Hybrid
and
DC
Termination
Si3014
Si3014 (SOIC or TSSOP)
RX
QE2
FILT
FILT2
REF
DCT
VREG
VREG2
REXT
REXT2
RNG1
RNG2
QB
QE
QE2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FILT2
FILT
RX
REXT
REXT2
REF
V REG2
V REG
DCT
IGND
C1B
RNG1
RNG2
QB
QE
Isolation
Interface
Isolation
Interface
ID0
ID1
G PIO_A
G PIO_B
Control
Interface
Ring Detect
Off-Hook
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
Si3038-DS201
Rev. 2.01 9/01
Copyright © 2001 by Silicon Laboratories
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