IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
G
ENERAL
D
ESCRIPTION
This document describes the specification for the
IDTF1951 Digital Step Attenuator. The F1951 is part of a
family of
Glitch-Free
TM
DSAs optimized for the demanding
requirements of communications Infrastructure. These
devices are offered in a compact 4x4 QFN package with
50 impedances for ease of integration into the radio
system.
F
EATURES
•
•
•
•
•
•
•
•
•
•
•
Glitch-Free
TM
, < 0.6 dB transient overshoot
Spurious Free Design
3V to 5V supply
Attenuation Error < 0.2 dB @ 2 GHz
Low Insertion Loss < 1.2 dB @ 2 GHz
Excellent Linearity +65 dBm IP3
I
Fast settling time, < 450 nsec
Class 2 JEDEC ESD (> 2kV HBM)
Serial Interface 31.5 dB Range
Stable Integral Non-Linearity over temperature
4x4 mm Thin QFN 24 pin package
C
OMPETITIVE
A
DVANTAGE
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The IDTF1951 is a
6-bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (+65 dBm IP3
I
.) The device has
pinpoint accuracy and settles to final attenuation value
within 400 nsec. Most importantly, the F1951 includes
IDT’s
Glitch-Free
TM
technology which results in less
than 0.6 dB of overshoot ringing during MSB transitions.
This is in stark contrast to competing DSAs that
glitch as
much as 10 dB
during MSB transitions (see p.10)
D
EVICE
B
LOCK
D
IAGRAM
Lowest insertion loss for best SNR
Glitch-Free
TM
when transitioning –
won’t damage PA or ADC
Extremely accurate with low distortion
TM
Glitch-Free
TM
RF
1
RF
2
A
PPLICATIONS
•
•
•
•
•
•
•
•
•
Base Station 2G, 3G, 4G, TDD radiocards
Repeaters and E911 systems
Digital Pre-Distortion
Point to Point Infrastructure
Public Safety Infrastructure
WIMAX Receivers and Transmitters
Military Systems, JTRS radios
RFID handheld and portable readers
Cable Infrastructure
V
DD
CLK SDI CS SDO
Bias
DEC
SPI
RST
O
RDERING
I
NFORMATION
Omit IDT
prefix
0.8 mm height
package
Tape &
Reel
P
ART
# M
ATRIX
Part#
F 1951
F1950
F1952
Freq range
100 - 4000
150 - 4000
100 – 4000
Resolution
/ Range
0.50 / 31.5
0.25 / 31.5
0.50 / 15.5
Control
Serial Only
Serial Only
Serial Only
IL
- 1 .2
-1.3
-0.9
Pinout
HITT
PE
HITT
IDTF1951NBGI8
RF product Line
Green
Industrial
Temp range
Glitch-Free
TM
Digital Step Attenuator
1
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
A
BSOLUTE
M
AXIMUM
R
ATINGS
V
DD
to GND
D[5:0], DATA, CLK,CSb,SDO, RSTb
RF Input Power (RF1, RF2) calibration and testing
RF Input Power (RF1, RF2) continuous RF operation
θ
JA
(Junction – Ambient)
θ
JC
(Junction – Case)
The Case is defined as the exposed paddle
Operating Temperature Range (Case Temperature)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s) .
-0.3V to +5.25V
-0.3V to 3.6V
+29 dBm
+23 dBm
+50°C/W
+3°C/W
T
C
= -40°C to +100°C
140°C
-65°C to +150°C
+260°C
Glitch-Free
TM
Digital Step Attenuator
2
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
IDTF1951 S
PECIFICATION
(31.5 dB Range)
Specifications apply at
V
DD
= +3.3V, f
RF
= 2000MHz,
T
C
= +25°C unless otherwise noted, EVkit losses are de-embedded (see p. 17)
Parameter
Logic Input High
Logic Input Low
Logic Current
Supply Voltage(s)
Supply Current
Temperature Range
Frequency Range
RF1, RF2 Return Loss
Minimum Attenuation
Maximum Attenuation
Minimum Gain Step
Phase Delta
Differential Non-Linearity
Integral Non-Linearity
Integral Non-Linearity
Comment
CLK, CSb, DATA, D[5:0], RSTb
CLK, CSb, DATA, D[5:0], RSTb
Sym.
V
IH
V
IL
I
IH,
I
IL
V
DD
I
DD
T
C
f
RF
S
11
, S
22
A
MIN
or
IL
A
MAX
LSB
Φ
∆
DNL
INL
1
INL
2
IP3I
1
IP3I
2
IP3I
3
min
2.3
-5
typical
max
3.6
0.7
+5
units
V
V
µA
V
mA
degC
MHz
dB
V
MODE
Main Supply
Total
Operating Range (Case)
Operating Range
dB(s11), dB(s22)
D[5:0] = [111111]
•
D[5:0] = [000000]
•
V
DD
= 3.3V
3.0 to 5.25
1.1
-40 to +100
100 to 4000
-22
1.2
32.2
32.5
0.50
33
0.08
0.03
0.21
+61
2
2
1
1.9
dB
dB
dB
deg
dB
Least Significant Bit
Phase change A
MIN
vs. A
MAX
Error: adjacent steps
Error: absolute to 14 dB
ATTN
Max Error vs. line (A
MIN
ref) to
31.5 dB ATTN [V
DD
= 3.3V]
0.34
0.38
dB
dB
D[5:0] = [111111] = A
MIN
D[5:0] = [100000] = A
15.5
Input IP3
D[5:0] = [000000] = A
MAX
P
IN
= +10 dBm per tone
50 MHz Tone Separation
V
DD
= 3.3V
+64
+61
+61
+59
+57
dBm
0.1 dB Compression
Please note ABS MAX
D[5:0] = [111010] = A
2.5
Baseline P
IN
= 20 dBm
Start LE rising edge > V
IH
End +/-0.10 dB Pout settling
15.5 – 16.0 transition
P
0.1
T
LSB
F
CLK
A
B
C
D
20
5
40
8
29
400
20
50
dBm
nsec
MHz
nsec
nsec
100
nsec
Cycles
Settling Time
Serial Clock Speed
Reset to Serial Setup
Serial Data Hold Time
CSb setup delay
Serial Data Out Delay
SPI 4 wire bus
SPI 4 wire bus
SPI 4 wire bus
SPI 4 wire bus
SPI 4 wire bus
8
8
S
PECIFICATION
N
OTES
:
1 – Items in min/max columns in
bold italics
are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Characterization
Glitch-Free
TM
Digital Step Attenuator
3
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
S
ERIAL
C
ONTROL
M
ODE
Data is clocked in LSB first via serial mode. Note the timing diagram below.
An RSTb pulse resets the shift register to [00000000]. If the RSTb pulse is followed immediately by a CSb pulse the
device will be set to
Maximum Attenuation.
Note
–
The IDTF1951 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device
is not being programmed. When CSb is high (> V
IH
), the CLK input is disabled and serial data (SDI) will not be clocked
into the shift register. It is recommended that CSb be pulled high (>V
IH
) when the device is not being programmed
S
ERIAL
R
EGISTER
T
IMING
D
IAGRAM
[S
INGLE
D
EVICE
]:
(Note the Timing Spec Intervals in
Blue)
S
ERIAL
R
EGISTER
T
IMING
D
IAGRAM
[T
WO OR MORE DEVICES
]:
The contents of the shift register is delayed by 8 clock cycles while CSb is low. This feature allows one to program
nd
multiple DSAs (in a MIMO transceiver for instance) with a single common CSb line by daisy-chaining the SDO of the 2
st
DSA to the SDI of the 1 DSA and so forth:
Glitch-Free
TM
Digital Step Attenuator
4
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
S
ERIAL
R
EGISTER
D
EFAULT
C
ONDITION
[F1951]:
When the device is first powered up, it will default to the
Maximum Attenuation
setting as described below:
Note that for the F1951 (High or 1) = Attenuation Stepped OUT. (0 or Low) = Attenuation Stepped IN.
100 MHz to 4000 MHz
Default Register Settings
0
R0
RSV
0
R1
RSV
0
D0
LSB
0
D1
0
D2
0
D3
0
D4
0
D5
MSB
S
ERIAL
R
EGISTER
T
IMING
T
ABLE
[F1951]:
Interval
Symbol
A
B
C
D
Description
Reset to Serial Setup Time
Serial Data Hold Time
CSb setup delay
Serial Data Out Delay
Min
Spec
20
5
40
8
Max
Spec
100
8
Units
nsec
nsec
nsec
Cycles
Glitch-Free
TM
Digital Step Attenuator
5
Rev2 April 2013
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