DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
G
ENERAL
D
ESCRIPTION
The IDTF1240 (0.5 dB steps) is an IF VGA for Diversity
Basestation receivers. The device offers significantly
better Noise and Distortion performance than currently
available devices. It is packaged in a compact 5x5
Thin QFN with 200 ohm differential input and output
impedances for ease of integration into the receiver
lineup.
F
EATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ideal for systems with high SNR requirements
20 dB typical Maximum Gain
31.5 dB gain control range
6 bit control
0.50 dB Gain Steps
Excellent Noise Figure = 4.0 dB
5mm x 5mm 32 pin package
200
Differential Matched Input
200
Differential Matched Output
No termination resistors required
NF degrades just 1.3 dB @ 10 dB below
Ma x G a i n
10 MHz – 500 MHz frequency range
Ultra-Linear:
IP3
O
+47 dBm
typical
Excellent 2
nd
Harmonic Rejection
Selectable Parallel or Serial Control
External current setting resistors
Very fast settling < 15 nsec
Individual Power Down Modes
Extremely Low Power:
80 mA / Chan
C
OMPETITIVE
A
DVANTAGE
The IDTF1240 IF VGA improves system SNR, especially
at lower gain settings. Via IDT’s proprietary FlatNoise
TM
technology both
IP3
O
& NF are kept virtually flat
while gain is backed off, enhancing SNR significantly
under high level interferer conditions, and greatly
benefiting 2G/3G/4G Multi-Carrier IF sampling receivers.
The fast-settling, parallel mode gain step of 0.50 dB
coupled with the excellent differential non-linearity allow
for SNR to be maximized further by targeting the
minimum necessary gain in small, accurate increments.
The matched output does not require a terminating
resistor, thus the gain and distortion performance are
preserved when driving Bandpass Anti-Alias filters.
See the ‘Applications Information’ section starting on
Page 19 for more details of the benefits of the F1240 in
IF sampling receivers.
D
EVICE
B
LOCK
D
IAGRAM
P
ART
# M
ATRIX
Part#
F1240
Range /
Step
20 to -11.5
0.5
20 to -11
1.0
IP3
O
47
IF freq
range
10 - 500
NF
4
Pinout
Compatibility
ATTN
In A
AMP
out A
NSM
Gain
Control
SPI
12
V
CC
F1241
47
10 - 500
4
ADI
V
DD
V
MODE
Decode
Logic
Bias
Control
2
STBY
A
STBY
B
I
SET
O
RDERING
I
NFORMATION
Omit IDT
prefix
0.8 mm height Tape &
Reel
package
ATTN
In B
AMP
out B
IDTF1240NBGI8
RF product Line
Green
Industrial
Temp range
IDT FlatNoise
TM
IF VGA
1
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
A
BSOLUTE
M
AXIMUM
R
ATINGS
V
CC
to GND
GA[5-0], GB[5-0], DATA, CSb, CLK, V
MODE
, STBY
A
, STBY
B
OUT_A-, OUT_A+, OUT_B-, OUT_B+
IN_A-, IN_A+, IN_B-, IN_B+
ISET_A, ISET_B to GND
RF Input Power (IN_A-, IN_A+, IN_B-, IN_B+) @ G
MAX
Continuous Power Dissipation
θ
JA
(Junction – Ambient)
θ
JC
(Junction – Case)
The Case is defined as the exposed paddle
Operating Temperature Range (Case Temperature)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s) .
-0.3V to +5.5V
-0.3V to (VCC_ + 0.25V)
-0.3V to (VCC_ + 0.25V)
-0.3V to +2.2V
-0.3V to +2.2V
+15 dBm
1.5W
+40°C/W
+3°C/W
T
C
= -40°C to +100°C
150°C
-65°C to +150°C
+260°C
Stresses above those listed above may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ESD Caution
This product features proprietary protection circuitry. However, it may be
damaged if subjected to high energy ESD. Please use proper ESD precautions
when handling to avoid damage or loss of performance.
T
RUTH
T
ABLE
Gain Set
Target
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
Gain
CodeWord
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
Code
Name
G
20
G
19.5
G
19
G
18.5
G
18
G
17.5
G
17
G
16.5
G
16
G
15.5
G
15
G
14.5
G
14
G
13.5
G
13
G
12.5
G
12
G
11.5
G
11
G
10.5
G
10
Gain Set
Target
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Gain
CodeWord
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
Code
Name
G
9.5
G
9
G
8.5
G
8
G
7.5
G
7
G
6.5
G
6
G
5.5
G
5
G
4.5
G
4
G
3.5
G
3
G
2.5
G
2
G
1.5
G
1
G
0.5
G
0
G
-0.5
Gain Set
Target
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
Gain
CodeWord
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Code
Name
G
-1
G
-1.5
G
-2
G
-2.5
G
-3
G
-3.5
G
-4
G
-4.5
G
-5
G
-5.5
G
-6
G
-6.5
G
-7
G
-7.5
G
-8
G
-8.5
G
-9
G
-9.5
G
-10
G
-10.5
G
-11
G
-11.5
IDT FlatNoise
TM
IF VGA
2
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
IDTF1240 S
PECIFICATION
Specified values apply at V
CC
= +5.0V,
f
RF
= 200MHz,
T
C
= +25°C,, V
MODE
> V
IH
(parallel mode), STBY
A
, STBY
B
= 3.3V or NC,
R34 & R36 =
3.83K
unless otherwise noted. EVkit transformer losses are de-embedded
Parameter
Logic Input High
Logic Input Low
Logic Current
Logic Current
Temperature
Voltage
Supply Current
Standby Current
Frequency Range
Frequency Range
1dB Gain Rolloff
Input Resistance
4
4
3
Comment
Symbol
V
IH
V
IL
min
2.0
0
-2
-10
typ
max
0.8
+2
+1
units
V
V
µA
µA
degC
GA[5-0], GB[5-0]
V
IH
= 3.45 V, V
IL
= 0V
I
IH,
I
IL
I
IH,
I
IL
T
CASE
V
CC
I
SUPP
I
STBY
f
RF
f
RF
BW
R
IN
R
OUT
G
20
or
G
MAX
G
-11.5
or
G
MIN
V
MODE
, STBY_A, STBY_B
V
IH
= 3.45 V, V
IL
= 0V
Operating Case Temp Range
All Supplies Operating Range
-40 to 100
4.75
5.00
160
2.3
50 to 400
5 to 560
400
200
200
5.25
176
5
1
V
mA
mA
MHz
MHz
MHz
Total, All V
CC
Total, All V
CC
STBY_A, STBY_B < V
IL
Low Distortion Range
IP3O > 40 dBm, Pout +3 dBm/Tone
Gain Set = G
20
Operating Range
Gain > 17 dB
With L1,L2,L3,L4 = 1500 nH
Frequency @ 1dB Gain
reduction vs. 100 MHz Gain
Differential ( > 10 dB RL)
Differential ( > 15 dB RL)
Output Resistance
Maximum Gain
Minimum Gain
18
20
-11.5
0.50
2.7
0.08
0.19
4.0
5.3
4.5
2
dB
-9
dB
dB
deg
dB
dB
dB
dB
dBm
dBm
5.8
Minimum Gain Step
Phase Error
Differential Gain Error
Integral Gain Error
Noise Figure
Noise Figure
Output IP3 –
Narrowband offset
Output IP3 –
Wideband offset
Parallel or Serial Mode
Maximum phase change
between G
MAX
and any state
down to G
-4
Between any two adjacent 0.5
dB steps
LSB
IPE
DNL
INL
NF
NF
BACK
IP3
O1
IP3
O2
42
Error vs. line (G
20
Ref)
At G
20
At Gain Set = 10 dB (G
10
)
Set G
MAX,
Pout = +3 dBm per tone
800 KHz Tone Separation
Set G
MAX,
20 MHz Tone Separation
Pout = +3 dBm per tone
46.5
45
IDT FlatNoise
TM
IF VGA
3
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
IDTF1240 S
PECIFICATION
(C
ONT
.)
Parameter
Output IP3 –
Mid Gain
2 Harmonic
Output IP2
1 dB Compression
Channel Isolation
nd
Comment
Set Gain = 10 dB (G
10
)
Pout = +3 dBm per tone
800 KHz Tone Separation
Set G
10,
F
RF
= 200 MHz
Pout = +3 dBm
Set G
10,
F
RF
= 190 MHz, 210 MHz
Pout = +3 dBm per tone
Symbol
IP3
O3
H2
IP2
H
P1dB
O
ISO
C
min
42
typ
44.5
-90
76
max
units
dBm
dBc
dBm
dBm
dBc
Measure @ G
20
OUT_B vs. OUT_A w/ IN_A input
200 MHz
16
60
19.7
69
Measured @ G
20
for both
channels
In Parallel Mode or In Serial Mode
from CSb high
Any two Adjacent 1dB Steps
+/-0.10 dB Pout settling
Settling Time
T
1dB
ctrl
F
CLOCK
T
MODE
12
nsec
Control Scheme
Serial Clock Speed
Parallel to Serial
Setup Time
Data to Clock Setup
SPI
TM
(V
MODE
= V
IL
or GND)
Parallel (V
MODE
= NC or V
IH
)
Both
20
100
50
MHz
ns
SPI 3 wire bus
Minimum Interval after V
MODE
is
pulled low to initiate serial
programming via a CSb
assertion
Minimum Interval between
valid data bit and Clock Rising
Edge
Minimum Interval after Clock
Rising Edge that Data Bit must
be held
CSb must be pulled low this
minimum interval BEFORE the
next rising clock edge
Minimum clock interval from
rising to falling edge
T
S
T
H
T
EN
T
W
5
ns
Data Hold Time
5
ns
Clock to CSb Setup
Clock Pulse Width
8
15
ns
ns
S
PECIFICATION
N
OTES
:
1 – Items in min/max columns in
bold italics
are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Centering
3 - VMODE, STBY_A, and STBY_B all have internal pullup resistors such that they float to > VIH
4 - Measured with 4:1 Transformers (see applications Circuit)
IDT FlatNoise
TM
IF VGA
4
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
S
ERIAL
M
ODE
Serial mode is selected by grounding V
MODE
(pin4) or pulling it to a voltage < V
IL
. In serial mode the IDTF1240
Ch_A and Ch_B gains can be programmed independently via the serial port by asserting Chip Select (CSb).
S
ERIAL
M
ODE
T
IMING
D
IAGRAM
H
IGH
L
EVEL
:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
Data Word
Latched into
Register
CS
Address Word A7 – A0
DATA
0
RSV
Data Word D7 – D0
0
0=A
1=B
1 = On
16 dB
0 = Off
0
0
0
0
0
8 dB
4 dB
2 dB
1 dB
0.5 dB
0
RSV
RSV RSV RSV RSV
RSV RSV
CH
EN
G5
MSB
1 = 16 dB
ATTN
G4
G3
G2
G1
G0
LSB
S
ERIAL
M
ODE
T
IMING
D
IAGRAM
Z
OOM
:
Ts
T
H
DATA
A7
A6
CLK
CS
T
EN
IDT FlatNoise
TM
IF VGA
5
Rev O Mar 2012
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