Si861x/2x Data Sheet
Low-Power Single and Dual-Channel Digital Isolators
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advantag-
es over legacy isolation technologies. The operating parameters of these products re-
main stable across wide temperature ranges and throughout device service life for ease
of design and highly uniform performance. All device versions have Schmitt trigger inputs
for high noise immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Ordering options include a choice of isolation ratings (2.5, 3.75 and 5
kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products are safety certified by UL, CSA, VDE, and CQC, and products in
wide-body packages support reinforced insulation withstanding up to 5 kV
RMS
.
Applications
• Industrial automation systems
• Medical electronics
• Hybrid electric vehicles
• Isolated switch mode supplies
• Isolated ADC, DAC
• Motor control
• Power inverters
• Communications systems
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 V
RMS
for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1 (reinforced insulation)
• VDE certification conformity
• Si862xxT options certified to reinforced VDE 0884-10
• All other options certified to IEC 60747-5-5 and reinforced 60950-1
• CQC certification approval
• GB4943.1
KEY FEATURES
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 V
RMS
isolation
• Reinforced VDE 0884-10, 10 kV surge-
capable (Si862xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
2.5 V Operation
• 1.5 mA per channel at 1 Mbps
• 3.5 mA per channel at 100 Mbps
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Precise timing (typical)
• 10 ns propagation delay
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C
• RoHS-compliant packages
• SOIC-16 wide body
• SOIC-8 narrow body
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Rev. 1.6
Si861x/2x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs
1, 2
Ordering Part
Number (OPN)
Si8610BB-B-IS
Si8610BC-B-IS
Si8610EC-B-IS
Si8610BD-B-IS
Si8610ED-B-IS
Si8620BB-B-IS
Si8620EB-B-IS
Si8620BC-B-IS
Si8620EC-B-IS
Si8620BD-B-IS
Si8620ED-B-IS
Si8621BB-B-IS
Si8621BC-B-IS
Si8621EC-B-IS
Si8621BD-B-IS
Si8621ED-B-IS
Si8622BB-B-IS
Si8622EB-B-IS
Si8622BC-B-IS
Si8622EC-B-IS
Si8622BD-B-IS
Si8622ED-B-IS
Number of
Inputs
VDD1 Side
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
Number of
Inputs
VDD2 Side
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Max Data Rate
(Mbps)
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Default
Output
State
Low
Low
High
Low
High
Low
High
Low
High
Low
High
Low
Low
High
Low
High
Low
High
Low
High
Low
High
Isolation
Rating (kV)
2.5
3.75
3.75
5.0
5.0
2.5
2.5
3.75
3.75
5.0
5.0
2.5
3.75
3.75
5.0
5.0
2.5
2.5
3.75
3.75
5.0
5.0
Temp (C)
Package
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
SOIC-8
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
SOIC-8
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8620BT-IS
Si8620ET-IS
Si8621BT-IS
Si8621ET-IS
Si8622BT-IS
Si8622ET-IS
2
2
1
1
1
1
0
0
1
1
1
1
150
150
150
150
150
150
Low
High
Low
High
Low
High
5.0
5.0
5.0
5.0
5.0
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
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Rev. 1.6 | 1
Si861x/2x Data Sheet
System Overview
2. System Overview
2.1 Theory of Operation
The operation of an Si861x/2x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si861x/2x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the trans-
mitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that de-
codes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si861x/2x Data Sheet
System Overview
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8610. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8610 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Si861x/2x Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in
Figure 3.1 Device Behavior during Normal Operation on
page 5,
where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following table to
determine outputs when power supply (VDD) is not present.
Table 3.1. Si86xx Logic Operation
V
I
Input
1, 2
H
L
X
5
VDDI State
1, 3, 4
P
P
UP
VDDO State
1, 3, 4
P
P
P
V
O
Output
1, 2
H
L
L
6
H
6
X
5
P
UP
Undetermined
Upon transition of VDDI from unpowered to powered, V
O
re-
turns to the same state as V
I
in less than 1 µs.
Upon transition of VDDO from unpowered to powered, V
O
re-
turns to the same state as V
I
within 1 µs.
Normal operation.
Comments
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default out-
put state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices,
the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/outputs.
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Rev. 1.6 | 4
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