EURO
QUARTZ
11.4 x 9.6 x 2.5mm 6 pad SMD VCXO
Frequency range 750kHz to 800MHz
LVPECL Output
Supply Voltage 3.3 VDC
Phase jitter 2.6ps typical (12kHz ~ 20MHz)
Pull range from ±30ppm to ±150ppm
DESCRIPTION
GPW62 VCXOs are packaged in 6 pad 7mm x 5mm SMD. Typical
phase jitter for GPW series VCXOs is 2.6ps. Output is LVPECL.
Applications include phase lock loop, SONET/ATM, set-top boxes,
MPEG , audio/video modulation, video game consoles and HDTV.
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
RMS Period Jitter:
Peak to Peak Jitter:
Phase Jitter 12kHz to 20MHz):
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
GPW62 PECL VCXO
750.0kHz to 800.0MHz
OUTLINE & DIMENSIONS
750.0kHz to 800.0MHz
3.3 VDC ±5%
LVPECL
4.3ps typical
27.0ps typical
2.6ps typical
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
Vdd-1.025V minimum
Vdd-0.880V maximum
Vdd-1.810V minimum
Vdd-1.620V maximum
From ±30ppm to ±150ppm
1.65 ±0.35 Volts
50W into Vdd or Thevenin equiv.
0.5ns typ., 0.7ns max.
20% Vdd to 80% Vdd
50% ±5%
10ms maximum, 5ms typical
25mA max.
65mA max.
100mA max.
2kV maximum
-55° to +150°C
±2ppm per year maximum
Fully compliant
Pulling Range:
Control Voltage Range:
Temperature Stability:
Output Load:
Rise/Fall Times:
Duty Cycle:
Start-up Time:
Current Consumption
<24MHz:
24.01 to 96MHz:
96.01 to 800MHz:
Static Discharge Protection:
Storage Temperature:
Ageing:
Enable/Disable:
RoHS Status:
FREQUENCY STABILITY
PHASE NOISE at 156.250MHz
Offset:
10Hz 100Hz
dBc/Hz:
-62
-92
1kHz
-120
10kHz
-132
100kHz 1MHz 10MHz
-128
-140
-150
PHASE NOISE at 155.520MHz
Offset:
10Hz 100Hz
dBc/Hz:
-60
-90
PART NUMBERING
Example:
1kHz
-115
10kHz
-125
100kHz 1MHz 10MHz
-119
-120
-140
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
ENABLE/DISABLE FUNCTION
Tristate Pad Output Status
Status
Not connected LVPECL and Complimentary LVPECL enabled
Below 0.3Vdd Both outputs are disabled (high impedance)
Above 0.7Vdd
Both outputs are enabled
3 GPW62 B-80N-60.000
Supply Voltage
3 = +3.3V
Series Designator
GPW62
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
FPGA/CPLD
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