Data Sheet
FEATURES
Parallel LVDS (DDR) outputs
In-band SFDR = 82 dBFS at 340 MHz (500 MSPS)
In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS)
1.1 W total power per channel at 500 MSPS (default settings)
Noise density = −153 dBFS/Hz at 500 MSPS
1.25 V, 2.50 V, and 3.3 V dc supply operation
Flexible input range
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Noise shaping requantizer (NSR) option for main receiver
function
Variable dynamic range (VDR) option for digital
predistortion (DPD) function
2 integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
Differential clock inputs
Integer clock divide by 1, 2, 4, or 8
Energy saving power-down modes
Small signal dither
135 MHz BW IF Diversity Receiver
AD6679
APPLICATIONS
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
GENERAL DESCRIPTION
The
AD6679
is a 135 MHz bandwidth mixed-signal intermediate
frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS
analog-to-digital converters (ADCs) and various digital signal
processing blocks consisting of four wideband DDCs, an NSR,
and VDR monitoring. It has an on-chip buffer and a sample-and-
hold circuit designed for low power, small size, and ease of use.
This product is designed to support communications applications
capable of sampling wide bandwidth analog signals of up to 2 GHz.
The
AD6679
is optimized for wide input bandwidth, high sampling
rates, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
FUNCTIONAL BLOCK DIAGRAM
AVDD1
(1.25V)
BUFFER
VIN+A
ADC
VIN–A
FD_A
FAST
DETECT
FD_B
V_1P0
BUFFER
VIN+B
ADC
VIN–B
VARIABLE
DYNAMIC RANGE
(×2)
SIGNAL
MONITOR
DATA
ROUTER
MUX
DIGITAL DOWN-
CONVERSION
(×4)
LVDS
OUTPUT
STAGING
LVDS
OUTPUTS
16
SIGNAL PROCESSING
D0±
D1±
D2±
D3±
D4±
D5±
D6±
D7±
D8±
D9±
D10±
D11±
D12±
D13±
DCO±
STATUS±
AVDD2
(2.50V)
AVDD3
(3.3V)
DVDD
(1.25V)
DRVDD
(1.25V)
SPIVDD
(1.22V TO 3.4V)
NOISE SHAPING
REQUANTIZER
(×2)
CLK+
CLK–
÷2
÷4
÷8
CLOCK
GENERATION
AND ADJUST
SPI CONTROL
FAST
DETECT
AD6679
SIGNAL
MONITOR
PDWN/STBY
AGND
SYNC±
SDIO
SCLK
CSB
DGND
DRGND
Figure 1.
Rev. B
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13059-001
AD6679
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Product Highlights ........................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications.......................................................................... 6
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 18
Thermal Characteristics ............................................................ 18
ESD Caution ................................................................................ 18
Pin Configurations and Function Descriptions ......................... 19
Typical Performance Characteristics ........................................... 25
Equivalent Circuits ......................................................................... 28
Theory of Operation ...................................................................... 30
ADC Architecture ...................................................................... 30
Analog Input Considerations.................................................... 30
Voltage Reference ....................................................................... 32
Clock Input Considerations ...................................................... 33
Power-Down/Standby Mode..................................................... 35
Temperature Diode .................................................................... 35
Virtual Converter Mapping ........................................................... 36
ADC Overrange and Fast Detect .................................................. 38
ADC Overrange (OR) ................................................................ 38
Fast Threshold Detection (FD_A and FD_B) ........................ 38
Signal Monitor ................................................................................ 39
Digital Downconverter (DDC) ..................................................... 40
DDC I/Q Input Selection .......................................................... 40
DDC I/Q Output Selection ....................................................... 40
DDC General Description ........................................................ 40
Frequency Translation ................................................................... 46
Data Sheet
General Description ................................................................... 46
DDC NCO Plus Mixer Loss and SFDR ................................... 47
Numerically Controlled Oscillator .......................................... 47
FIR Filters ........................................................................................ 49
Overview ..................................................................................... 49
Half-Band Filters ........................................................................ 49
DDC Gain Stage ......................................................................... 51
DDC Complex to Real Conversion ......................................... 51
DDC Example Configurations ................................................. 52
Noise Shaping Requantizer (NSR) ............................................... 56
Decimating Half-Band Filter .................................................... 56
NSR Overview ............................................................................ 56
Variable Dynamic Range (VDR) .................................................. 59
VDR Real Mode.......................................................................... 60
VDR Complex Mode ................................................................. 60
Digital Outputs ............................................................................... 62
Timing.......................................................................................... 62
Data Clock Output ..................................................................... 62
ADC Overrange .......................................................................... 62
Multichip Synchronization............................................................ 64
SYNC± Setup and Hold Window Monitor ............................. 65
Test Modes ....................................................................................... 67
ADC Test Modes ........................................................................ 67
Serial Port Interface (SPI) .............................................................. 68
Configuration Using the SPI ..................................................... 68
Hardware Interface ..................................................................... 68
SPI Accessible Features .............................................................. 68
Memory Map .................................................................................. 69
Reading the Memory Map Register Table............................... 69
Memory Map Register Table ..................................................... 70
Applications Information .............................................................. 80
Power Supply Recommendations............................................. 80
Outline Dimensions ....................................................................... 81
Ordering Guide .......................................................................... 81
Rev. B | Page 2 of 81
Data Sheet
REVISION HISTORY
4/16—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 8
Changes to Table 5 and Figure 3 ..................................................... 9
Changes to Figure 4 Caption .........................................................10
Changes to Figure 5 Caption .........................................................11
Changes to Figure 6 Caption .........................................................12
Changes to Figure 7 Caption .........................................................13
Changes to Figure 8 Caption .........................................................14
Changes to Figure 10 ......................................................................16
Changes to Table 6 ..........................................................................18
Changes to Input Clock Divider Section .....................................34
Added Virtual Converter Mapping Section and Table 12;
Renumbered Sequentially ..............................................................36
Added Figure 60; Renumbered Sequentially ...............................37
Changes to Table 35 ........................................................................62
Changes to Datapath Soft Reset Section ......................................69
Changes to Table 41 ........................................................................70
AD6679
9/15—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 3
Changes to Figure 12 ...................................................................... 18
Changes to Figure 13 ...................................................................... 20
Changes to Figure 14 ...................................................................... 22
Changes to ADC Test Modes......................................................... 63
5/15—Revision 0: Initial Version
Rev. B | Page 3 of 81
AD6679
The analog input and clock signals are differential inputs. The
ADC data outputs are internally connected to four DDCs
through a crossbar mux. Each DDC consists of up to five
cascaded signal processing stages: a 12-bit frequency translator
(NCO) and up to four half-band decimation filters.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes, selectable via the
serial port interface (SPI). With the NSR feature enabled, the
outputs of the ADCs are processed such that the
AD6679
supports
enhanced SNR performance within a limited portion of the
Nyquist bandwidth while maintaining a 9-bit output resolution.
Each ADC output is also connected internally to a VDR block.
This optional mode allows full dynamic range for defined input
signals. Inputs that are within a defined mask (based on DPD
applications) pass unaltered. Inputs that violate this defined
mask result in the reduction of the output resolution.
With VDR, the dynamic range of the observation receiver is
determined by a defined input frequency mask. For signals
falling within the mask, the outputs are presented at the
maximum resolution allowed. For signals exceeding defined
power levels within this frequency mask, the output resolution
is truncated. This mask is based on DPD applications and
supports tunable real IF sampling, and zero IF or complex IF
receive architectures.
Operation of the
AD6679
between the DDC, NSR, and VDR
modes is selectable via SPI-programmable profiles.
In addition to the DDC blocks, the
AD6679
has several functions
that simplify the AGC function in a communications receiver.
The programmable threshold detector allows monitoring of the
Data Sheet
incoming signal power using the fast detect control bits in
Register 0x245 of the ADC. If the input signal level exceeds the
programmable threshold, the fast detect indicator goes high.
Because this threshold indicator has low latency, the user can
quickly reduce the system gain to avoid an overrange condition
at the ADC input. In addition to the fast detect outputs, the
AD6679
also offers signal monitoring capability. The signal
monitoring block provides additional information about the
signal that the ADC digitized.
The output data is routed directly to the one external
14-bit LVDS output port, supporting double data rate (DDR)
formatting. An external data clock and a clock status bit are offered
for data capture flexibility.
The
AD6679
has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V capable 3-wire SPI.
The
AD6679
is available in a Pb-free, 196-ball BGA_ED, and is
specified over the −40°C to +85°C industrial temperature range.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Wide full power bandwidth IF sampling of signals up to
2 GHz.
Buffered inputs with programmable input termination
eases filter design and implementation.
Four integrated wideband decimation filters and NCO
blocks support multiband receivers.
Flexible SPI controls various product features and
functions to meet specific system requirements.
Programmable fast overrange detection and signal
monitoring.
Programmable fast overrange detection.
12 mm × 12 mm, 196-ball BGA_ED.
Rev. B | Page 4 of 81
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD6679
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference (V
REF
), A
IN
= −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Voltage
INPUT REFERRED NOISE
V
REF
= 1.0 V
ANALOG INPUTS
Differential Input Voltage Range (Internal V
REF
= 1.0 V)
Common-Mode Voltage (V
CM
)
Differential Input Capacitance
1
Analog Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
DVDD
DRVDD
SPIVDD
I
AVDD1
I
AVDD2
I
AVDD32
I
DVDD
(Default SPI—NSR Mode)
I
DVDD
(VDR Mode)
I
DRVDD3
I
SPIVDD
POWER CONSUMPTION
Total Power Dissipation
Default SPI—NSR Mode
3
VDR Mode
3
Power-Down Dissipation
Standby
4
1
2
Temperature
Min
14
Typ
Max
Unit
Bits
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
−0.3
−6.5
−0.6
−4.5
Guaranteed
0
+0.3
0
0.3
0
+6.5
0
5.0
±0.5
+0.7
±2.5
+5.0
±3
−39
1.0
2.04
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
V
LSB rms
1.46
2.06
2.05
1.5
2
1.25
2.50
3.3
1.25
1.25
1.8
464
396
89
141
117
110
5
2.06
V p-p
V
pF
GHz
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
1.22
2.44
3.2
1.22
1.22
1.22
1.28
2.56
3.4
1.28
1.28
3.4
503
455
100
164
138
123
6
Full
Full
Full
Full
2.2
2.16
0.71
1.4
2.37
2.34
W
W
W
W
Differential capacitance is measured between the VIN+x and VIN−x pins (x = A, B).
AVDD3 current changes based on the Buffer Control 1 setting (see Figure 46).
3
Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.
4
Standby can be controlled by the SPI.
Rev. B | Page 5 of 81
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