internally by a dedicated comparator circuit, which employs an internal bandgap
voltage reference nominally equal to 1.25V. Every time V
DD
falls below the threshold
voltage, nominally 4.65V, RESET_OD and WDO outputs are forced low. (See WDO
and RESET_OD descriptions.) (Figure 4.)
ASIC Ground.
This pin should be tied to ground and establishes the reference for
voltage detection.
Threshold detector input.
Voltage on this input is fed directly to an internal
comparator where it is compared to the bandgap voltage reference of 1.25vV It can
be used for detection of low battery or power failure of voltage supplies other than
V
DD
. When voltage at PFI input drops below its threshold value of 1.25V. PFO output
is forced low, otherwise, stays high.
Threshold detector output.
Active low. It responds directly to PFI input. If PFI
voltage is below the bandgap reference voltage, PFO is low. If PFI is above the
reference voltage, PFO output is high.
Watchdog timer input pin.
This pin is typically used to monitor microprocessor
activity. It can assume three states: low, high and float. If WDI is floating or connected
to a high impedance three state buffer, the watchdog timer is not active, and the
corresponding watchdog output WDO is high. Watchdog timer is also not active any
time RESET_OD is low. Providing that RESET_OD is not asserted, any change of
state at WDI that is longer than 50ns will start the timer, or restart it, if the timer is
already running (Figure 3.). If there is no activity within the timeout period, nominally
1.6sec, the timer will stop running and WDO output will go low (Figure 3).
Reset output.
Active low open drain output. This pin is pulled up with a resistor
consistant with the sink and voltage current as specified in the electrical characteristics
table. This output responds to both: V
DD
monitoring circuits and the manual reset
input MR.
On power up, RESET_OD is guaranteed to be logic low for all V
DD
values from 1.2V
up to the reset threshold, nominally 4.65V. Once this threshold is reached, an internal
RESET_OD timer is activated. During the countdown RESET_OD output is kept low.
It is raised high upon completion of countdown, typically after 200ms. If a brown out
condition occurs during the reset timer countdown, the reset timer would be reset and
another countdown would start after V
DD
levels were restored above the reset
threshold. On power down, when V
DD
falls below the threshold voltage, RESET_OD
goes low and is guaranteed to stay low until V
DD
drops below 1.2V.
If MR is asserted low, RESET_OD is forced low and the reset timer is kept reset.
When MR is released high, the timer is activated and RESET_OD is kept low until
completion of the reset timeout, when it is raised high.
2
VDD
3
4
GND
PFI
Supply
Analog Input
5
PFO
Digital Output
6
WDI
Digital Input
7
RESET_OD
Open Drain
Digital Output
2
Number
8
Pins
WDO
Type
Digital Output
Description
Watchdog output.
Active low. This pin is usually connected to a non-maskable
interrupt input of a microprocessor. On power up, WDO responds to V
DD
monitoring
circuitry. It stays low until the reset threshold, 4.65V nominally, is reached. At that
point, WDO is raised high. The internal watchdog timer is activated after RESET_OD
is released. If there is no activity on WDI input, WDO goes low after the watchdog
timer times out, which is typically after 1.6sec. Any activity on WDI will force WDO
output to go high and the watchdog timer will be activated. If WDI is floating or
connected to a high impedance buffer output, the timer is kept in a reset state and
WDO stays high. When VDD drops below 4.65V, WDO goes low regardless of
whether the watchdog timer has timed out or not. RESET_OD goes low
simultaneously which prevents an interrupt.
If WDI input is left unconnected, WDO can be used as a low line output. Since a
floating WDI disables the internal watchdog timer, WDO goes low when V
DD
drops
below 4.65V, thus, functioning as a low line output. (Figure 4.)
MR
1
2
8
7
WDO
VDD
RESET_OD
UT01VS50D
GND
3
4
6
5
WDI
PFI
PFO
Figure 2. UT01VS50D Pin Configuration
3
OPERATIONAL ENVIRONMENT
PARAMETER
Total Ionizing Dose (TID)
Single Event Latchup Immune (SEL)
Single Event Transient Immune (SET)
LIMIT
300
<110
<80
UNITS
krad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to GND)
SYMBOL
V
DD
T
J
T
P
D
V
in
T
iead
θ
JC
V
ESD
Voltage supply
Maximum junction temperature
Storage temperature
Power dissipation
Input voltages
Lead Temperature (soldering, 10 seconds)
Thermal resistance, junction-to-case
ESD
HBM
PARAMETER
LIMITS
7.2
175
-65 to +150
2.5
-0.3V to (V
DD
+0.3V)
+300
15
1000
UNITS
V
°C
°C
W
V
°C
°C/W
V
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
GND
PARAMETER
Positive supply voltage
Case temperature range
Negative supply voltage
LIMITS
4.75 to 5.5
-55 to +125
0.0
UNITS
V
°C
V
4
ELECTRICAL CHARACTERISTICS
1,2
(V
DD
= 4.75V to 5.5V:-55°C < T
C
< +125°C)
SYMBOL
Power Supply
I
DD
V
DD
supply current
V
DD
=5.5V
530
μA
PARAMETER
CONDITION
MIN
MAX
UNIT
Digital Inputs and Outputs (MR, RESET_OD, WDI, WDO, PFO)
京公网安备 11010802033920号
EEWORLD
