Standard Products
UT699E 32-bit Fault-Tolerant
SPARC
TM
V8/LEON 3FT Processor
Datasheet
March 2015
www.aeroflex.com/LEON
FEATURES
Backward compatible with the UT699
Supports up to 100MHz clock rate
Separate instruction and data cache architecture
High-performance pipelined IEEE-754 FPU
Enhanced pipeline with 1.2 DMIPS / MHz performance
Implemented on 130nm CMOS technology
Internally configured clock network
Power saving 1.2V core power supply
3.3V I/O compatibility
On-board programmable timers and interrupt controllers
SEU hardened-by-design flip-flops and memory cells
10/100 Base-T Ethernet port for VxWorks development
Integrated PCI 2.2 compatible core
Four integrated multi-protocol SpaceWire nodes that
support the RMAP protocol
Two CAN 2.0 compliant bus interfaces
Multifunctional memory controller
-55 C to +105 C temperature range
Operational environment:
- Intrinsic total-dose: 100 krad(Si)
- SEL Immune
≤
110 MeV-cm
2
/mg
Packaging options:
- 484-pin Ceramic Land Grid, Column Grid and Ball
Grid Array packages
Standard Microcircuit Drawing 5962-13237
- QML Q, Q+, and V (Pending)
Applications
- Nuclear power plant controls
- Critical transportation systems
- High-altitude avionics
- Medical electronics
- X-Ray cargo scanning
- Spaceborne computer
- System controller boards
- Avionics processing boards
o
o
INTRODUCTION
The UT699E is an enhanced version of the UT699 featuring a
seven stage pipelined monolithic, high-performance, fault-
tolerant SPARC
TM
V8/LEON 3FT Processor. L1 cache has
been increased to 16kB for both instruction and data caches.
Performance is increased to 1.2 DMIPS / MHz. RMAP protocol
is supported for all four SpaceWire ports. Other enhancements
include cache snooping. The UT699E provides a 32-bit master/
target PCI interface, including a 16 bit user I/O interface for
off-chip peripherals. A compliant 2.0 AMBA bus interface
integrates the on-chip LEON 3FT, SpaceWire, Ethernet,
memory controller, cPCI, CAN bus, and programmable
interrupt peripherals.
The UT699E is SPARC V8 compliant; therefore, developers
may use industry standard compilers, kernels, and development
tools. A full software development suite is available including
a C/C++ cross-compiler system based on GCC and the Newlib
embedded C-library. Software developed for the UT699 will be
100% compatible with the UT699E.
BCC includes a small run-time kernel with interrupt support
and Pthreads library. For multi-threaded applications, a
SPARC
TM
compliant port of the eCos real-time kernel, RTEMS
4.10, and VxWorks 6.x is supported.
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Aeroflex Microelectronics Solutions - HiRel
1.0 Introduction
The UT699E LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates
the SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA
(Advanced Microcontroller Bus Architecture) interconnect. This bus is comprised of the AHB (Advanced High-speed Bus) which is
used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.
IEEE754
FPU
MUL/DIV
LEON 3FT
4x4K
D-cache
4x4K
I-cache
Debug
Support Unit
Serial/JTAG
Debug Link
4x SpW
PCI
Bridge
CAN-2.0
MMU
AHB interface
AHB Ctrl
Memory
Controller
AMBA AHB
AMBA APB
UART
8/16/32-bits memory bus
Timers
IrqCtrl
I/O port
Ethernet
MAC
AHB/APB
Bridge
512 MB
PROM
256 MB
I/O
Up t o1GB
SRAM
Up to 1GB
SDRAM
Figure 1. UT699E Functional Block Diagram
The LEON 3FT architecture includes the following peripheral blocks:
• LEON3 SPARC V8 integer unit with 16kB instruction cache and 16kB of data cache
• IEEE-754 floating point unit
• Debug support unit
• UART, JTAG, SpaceWire, and PCI debug links
• 8/16/32-bit memory controller with EDAC for external PROM and SRAM
• 32-bit SDRAM controller with EDAC for external SDRAM
• Timer unit with three 32-bit timers and watchdog
• Interrupt controller for 15 interrupts in two priority levels
• 16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources
• Up to four SpaceWire links with RMAP on all channels
• Up to two CAN controllers
• Ethernet with support for MII
• cPCI interface with 8-channel arbiter
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Aeroflex Microelectronics Solutions - HiRel
Pin Name
Direction
Pin
Number
484 CLGA
Reset
Value
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
Description
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[17]
ADDR[18]
ADDR[19]
ADDR[20]
ADDR[21]
ADDR[22]
ADDR[23]
ADDR[24]
ADDR[25]
ADDR[26]
ADDR[27]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AA7
AB6
W8
AB7
Y8
AA8
W9
AB8
Y9
W10
AB9
Y10
AA9
W11
AA10
Y11
AB10
AB11
AA11
Bit 9 of the address bus
Bit 10 of the address bus
Bit 11 of the address bus
Bit 12 of the address bus
Bit 13 of the address bus
Bit 14 of the address bus
Bit 15 of the address bus
Bit 16 of the address bus
Bit 17 of the address bus
Bit 18 of the address bus
Bit 19 of the address bus
Bit 20 of the address bus
Bit 21 of the address bus
Bit 22 of the address bus
Bit 23 of the address bus
Bit 24 of the address bus
Bit 25 of the address bus
Bit 26 of the address bus
Bit 27 of the address bus
2.3 Data Bus
Pin
Number
484 CLGA
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
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Ver. 1.5.0
I/O
I/O
I/O
I/O
I/O
W12
W13
Y12
AA13
AA12
high-z
high-z
high-z
high-z
high-z
Bit 0 of the data bus
Bit 1 of the data bus
Bit 2 of the data bus
Bit 3 of the data bus
Bit 4 of the data bus
Pin Name
Direction
Reset
Value
Description
4
Aeroflex Microelectronics Solutions - HiRel
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