Standard ICs
Picture cell driver for STN (LCD driver)
BU9716BK / BU9716BKV
The BU9716BK and BU9716BKV are man-machine interface ICs designed for applications such as multi-media
portable terminals.
Specifically, these products are used as driver ICs for operating mode display LCD panels in portable terminals,
household appliances, and other similar products. The number of display cells includes 32 segments and 3 com-
mons, enabling drive of up to 96 cells.
•
Applications terminals, POS terminals, ECR
Multi-media portable
terminals, short wave radios, telephones, cameras,
VCRs, movie projectors, car audio systems, and others
•
Features segment outputs and 3 common outputs
1) Up to 32
can be displayed, for a total of 96 segments.
2) 1 / 3 duty display.
3) Either 1 / 2 or 1 / 3 can be selected for power supply
for LCD display.
•
Absolute maximum ratings (Ta = 25°C, V
Parameter
Power supply voltage
Power dissipation
Input voltage
Operating temperature
Storage temperature
BU9716BK
BU9716BKV
V
DD
Pd
V
IN
Topr
Tstg
SS
= 0V)
Limits
– 0.3 ~ + 7.0
500
∗
1
400
∗
2
– 0.3 ~ V
DD
+ 0.3
– 40 ~ + 85
– 55 ~ + 125
Unit
V
mW
V
°C
°C
Symbol
∗
1 Reduced by 5mW for each increase in Ta of 1°C over 25°C .
∗
2 Reduced by 4mW for each increase in Ta of 1°C over 25°C .
•
Recommended operating conditions (Ta = 25°C, V
Parameter
Power supply voltage
Input voltage
Symbol
V
DD
V
DD1
V
DD2
Min.
4.5
0
0
SS
= 0V)
Max.
5.5
V
DD
V
DD
Unit
V
V
V
Typ.
—
2 / 3V
DD
1 / 3V
DD
1
Standard ICs
BU9716BK / BU9716BKV
•
Block diagram
V
DD1
V
DD2
LCD Power
RES
CS
DI
CK
CTRL Logic
DATA Latch
OSC
OSC
Common Driver
Segment Driver
S1
S2
S3
S4
S30
S31
S24
S23
COM1
COM2
COM1
•
Pin assignments
COM1
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
33
COM2
COM3
RES
V
DD
V
DD1
V
DD2
V
SS
OSC
CS
CK
DI
44
1
11
12
34
23
22
S22
S21
S20
S19
S18
COM2
COM3
RES
V
DD
V
DD1
V
DD2
V
SS
OSC
CS
CK
DI
N.C.
48
37
COM3
36
25
24
N.C.
S22
S21
S20
S19
S18
BU9716BK
S17
S16
S15
S14
S13
S12
BU9716BKV
N.C.
S32
S31
S30
S29
S28
S27
S26
S25
S32
S17
S16
S15
S14
S13
13
S12
1
12
S5
S5
2
N.C.
S10
S11
S10
S11
S1
S2
S3
S4
S6
S7
S8
S9
S1
S2
S3
S4
S6
S7
S8
S9
Standard ICs
BU9716BK / BU9716BKV
•
Pin descriptions (BU9716BK)
Pin No. Pin name I / O
1 - 32
33
34
35
36
41
42
43
44
38
39
S1 - S32
COM1
COM2
COM3
RES
OSC
CS
CK
DI
V
DD1
V
DD2
O
Function
Output pin for segment data. Outputs consistent LCD drive voltage to the
data corresponding to COM1 to COM3.
Common driver output. The frame frequency is f
C
= (f
OSC
/ 384) Hz
Processing
when not
used
OPEN
O
OPEN
I
—
I
I
I
—
—
Reset input. At RES = L, internal data (including control data) is reset.
Oscillator pin (for common and segment alternating waveforms)
Chip select input. At CS = H, data can be transferred.
Synchronous clock input for serial data transfer
Serial data input
Internal reference voltage for LCD drive. In 1 / 2 bias mode, this is connected to V
DD2
.
Internal reference voltage for LCD drive. In 1 / 2 bias mode, this is connected to V
DD1
.
V
DD
V
SS
V
SS
V
SS
V
SS
OPEN
OPEN
•
Electrical characteristics (unless otherwise noted, Ta = 25°C, V
Parameter
Input high level voltage
Input low level voltage
Input high level current
Input low level current
Output high level voltage
Symbol
V
IH
V
IL
I
IH
I
IL
V
SOH
V
COH
V
SOL
V
COL
V
CM1
V
SM1
Intermediate output voltage
V
CM2
V
SM2
V
CM3
Power supply current
I
Q
I
DD
Min.
0.8V
DD
0
0
0
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
V
DD
– 1.0
V
DD
– 1.0
1.0
1.0
1 / 2V
DD
±
1.0
2 / 3V
DD
±
1.0
2 / 3V
DD
±
1.0
1 / 3V
DD
±
1.0
1 / 3V
DD
±
1.0
30
100
DD
= 4.5V to 5.5V, V
SS
= 0V)
Unit
V
V
µA
µA
V
V
V
V
V
V
V
V
V
µA
µA
Conditions
CS, CK, DI, RES
CS, CK, DI, RES
CS, CK, DI, RES, V
I
= V
DD
CS, CK, DI, RES, V
I
= V
SS
S1 ~ S32, I
O
= – 20µA
COM1 ~ COM3, I
O
= – 100µA
S1 ~ S32, I
O
= – 20µA
COM1 ~ COM3, I
O
= – 100µA
COM1 ~ COM3, 1 / 2Bias
S1 ~ S32, 1 / 3Bias
COM1 ~ COM3, 1 / 3Bias
S1 ~ S32, 1 / 3Bias
COM1 ~ COM3, 1 / 3Bias
Low-power mode
f
OSC
= 38kHz
Max.
V
DD
0.2V
DD
6.0
6.0
—
—
—
—
—
—
—
—
—
70
300
Output low level voltage
3
Standard ICs
BU9716BK / BU9716BKV
•
Electrical characteristics otherwise noted, Ta = 25°C, V
AC characteristics (unless
Parameter
Recommended external resistance
Recommended external capacitance
Guaranteed oscillation range
Data setup time
Data hold time
CS setup time
CS hold time
CK "H" pulse width
CK "L" pulse width
Rise time
Fall time
Symbol
R
C
f
OSC
t
DS
t
DH
t
CS
t
CH
t
CKH
t
CKL
t
r
t
f
DD
= 4.5V to 5.5V, V
SS
= 0V)
Pin
OSC
OSC
OSC
CK, DI
CK, DI
Min.
—
—
19
100
100
100
100
100
100
—
—
Typ.
47
1000
38
—
—
—
—
—
—
—
—
Max.
—
—
76
—
—
—
—
—
—
300
300
Unit
kΩ
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
CS, CK
CS, CK
CK
CK
CS, CK, DI
CS, CK, DI
AC timing waveform
(1) When CK is stopped at “L”
0.8V
DD
CS
t
CS
t
CKH
t
CKL
t
CH
0.2V
DD
0.8V
DD
CK
t
DS
0.5V
DD
t
DH
0.5V
DD
0.8V
DD
0.2V
DD
t
r
t
f
DI
(2) When CK is stopped at “H”
0.8V
DD
CS
t
CS
t
CKH
t
CKL
t
CH
0.2V
DD
CK
0.2V
DD
t
DS
0.5V
DD
t
DH
0.5V
DD
0.8V
DD
0.2V
DD
t
r
t
f
DI
4
Standard ICs
BU9716BK / BU9716BKV
I
DD,
I
Q
V
DD
SW
4
CS, CK
DI, RES
S1 ~ S32
1
SW
3
V
DD1
2
0.047µF
V
DD2
OSC
V
SS
1000pF, 47kΩ
COM1 ~ COM3
1
2
SW
2
SW
1
1
2
3
V
CM1,
V
CM2,
V
CM3
V
SM1,
V
SM2
I
O
V
V
SOH,
V
SOL
V
COH,
V
COL
V
V
1
A
•
Measurement circuit
P. G.
A
I
IH,
L
H
V
2
1
2
0.047µF
GND
GND
∗
P. G.: Control signal generator for programmable signal generator, etc.
Fig.1
Measurement conditions
Parameter
Input high level voltage
Input low level voltage
Input high level current
Input low level current
Output high level voltage
Symbol
V
IH
V
IL
I
IH
I
IL
V
SOH
V
COH
V
SOL
V
COL
V
CM1
V
SM1
Intermediate output voltage
V
CM2
V
SM2
V
CM3
Current dissipation
AC characteristics
I
Q
I
DD
2
2
1
SW1
2
SW2
—
SW3
—
SW4
1
Conditions
Set as P.G. input voltage;
mode switching test
V
2
= V
DD
V
2
= V
SS
Pattern 1, I
O
= – 20µA
Pattern 1, I
O
= – 100µA
Pattern 2, I
O
= 20µA
Pattern 2, I
O
= 100µA
Pattern 3
Pattern 4
1
1
Pattern 4
Pattern 5
Pattern 5
—
—
1
1
Pattern 6
Test after power on
Used as P.G. input condition
2
—
1
2
1
2
2
1
2
1
2
—
—
—
2
3
1
1
Output low level voltage
3
2
2
1
Measurement pattern
CS
DI
CK
CS
DI
CK
CS
DI
CK
Pattern 1
Fig.2
CS
DI
CK
CS
DI
CK
Pattern 2
Fig.3
CS
DI
CK
Pattern 3
Fig.4
Pattern 4
Fig.5
Pattern 5
Fig.6
Pattern 6
Fig.7
5
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