SN74AHC541DGVRG4 datasheet, PDF

SN74AHC541DGVRG4: DescriptionOctal Buffers/Drivers With 3-State Outputs 20-TVSOP -40 to 125; Categorylogic logic; File Size1MB，30 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

Stay tuned Parametric

SN74AHC541DGVRG4 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	SN74AHC541DGVRG4	-	-	View	Buy Now

Octal Buffers/Drivers With 3-State Outputs 20-TVSOP -40 to 125

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	TSSOP, TSSOP20,.25,16
Contacts	20
Reach Compliance Code	compli
Factory Lead Time	6 weeks
Other features	WITH DUAL OUTPUT ENABLE
Control type	ENABLE LOW
Counting direction	UNIDIRECTIONAL
series	AHC/VHC/H/U/V
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25,16
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TR
Peak Reflow Temperature (Celsius)	260
power supply	2/5.5 V
Maximum supply current (ICC)	0.02 mA
Prop。Delay @ Nom-Su	8 ns
propagation delay (tpd)	12 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

Advertising lights: [align=center][align=center][size=3][font=宋体]4. Shift the advertising light left and right[/font][/size][/align][/align][size=3][font=宋体]1. Experimental task[/font][/size] [size=3][font=宋体]Shift a sin...; liuyong1989 Power technology

Using PLD internal phase-locked loop to solve system design problems: [b]Abstract: [/b]From the perspective of the entire application system, understand and analyze the phase-locked loop inside the PLD; on this basis, deeply analyze the phase-shift structure of the phas...; 呱呱 FPGA/CPLD

I heard there are a lot of talented people here ~ I came here to ask for help! ! ! ! ! ! ! ! ! ! ! !: It's about a digital password lock made with vhdl. The specific requirements are as follows: 1. 4-digit password decimal number (0-9) 2. Password setting key, unlock key, clear screen key 3. Display: ...; clnemo Embedded System

20 analog circuits that engineers should master: Take a look See how much you know...; heningbo Analog electronics

Take a look at the power management chip of Xiaomi Box. Do you know this company?: Recently, I was looking for a suitable power supply solution for the company's box design. My friends at Shiqiang recommended the Ricoh solution (RP200x, a voltage stabilization circuit solution with ...; 馬儿菲特 Power technology

What is the gpio current and pull-up/pull-down resistors for nRF24Le1?: I looked at the data sheet, but I didn't find out what the gpio drive current is (13mA?), and what size pull-up/pull-down resistor should be connected (22K?)...; leo121 RF/Wirelessly

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components