I642 datasheet, PDF - EEWORLD Datasheet

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I642: Description3.2 mm x 2.5 mm Ceramic Package SMD VCXO LVCMOS / LVPECL / LVDS; File Size114KB，3 Pages; ManufacturerILSI; Websitehttp://www.ilsiamerica.com

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I642 Overview

3.2 mm x 2.5 mm Ceramic Package SMD VCXO LVCMOS / LVPECL / LVDS

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3.2 mm x 2.5 mm Ceramic Package SMD VCXO

LVCMOS / LVPECL / LVDS

I642 Series

Product Features

Small Surface Mount Package

Fast Sample Delivery

Pb Free/ RoHS Compliant

Leadfree Processing

Applications

xDSL

Broadcast Video

Wireless Base Stations

Sonet /SDH

WiMAX/WLAN

Server and Storage

Ethernet/LAN/WAN

Optical modules

Clock and data recovery

FPGA/ASIC

Backplanes

GPON

3.20±0.10

Marking

2.50±0.10

Frequency

LVCMOS

LVPECL

LVDS

Output Level

LVCMOS

LVPECL

LVDS

Duty Cycle

LVCMOS

LVPECL

LVDS

Rise / Fall Time

LVCMOS

LVPECL

LVDS

Output Load

LVCMOS

LVPECL

LVDS

Frequency Stability

Supply Voltage (Vcc)

Aging

Current

10.000MHz to 250.000MHz

10.000MHz to 1500.000MHz

Logic “0” = 10% of Vcc max, Logic “1” = 90% of Vcc min

Logic “0”= Vcc-1.62V max., Logic “1” = 1.02 V min

VOD=(Diff. Output) 350mV Typ.

50% ±5% @ 50% of Vcc

50% ±5% @ 50%*

2.0 ns max. (10% to 90%)*

0.8 ns max. (20% to 80%)*

.70

1.00±0.15

.60

TYP

1.30

TYP

1.60

2.30

Linearity

Pullability

Control Voltage

Input Impedance

Phase Jitter (RMS)

At 12kHz to 20 MHz

Operating Temp. Range

Storage Temp. Range

15pF



to Vcc - 2.0 VDC

RL=100

/CL=

5pF

See Table Below

+3.30 VDC ± 5%, +2.50 VDC ± 5%

±3.0 ppm max per year

HCMOS = 45 mA max

LVPECL = 90 mA max

LVDS = 35 mA max

10% max.

See Table Below

1.65 VDC ± 1.65 VDC @ 3.3V

1.25 VDC ± 1.25 VDC @ 2.5V

50K



min.

0.9 ps typical

See Table Below

-40



C to +85



1.80

.90

.80

Suggested Land Pattern

PIN CONNECTIONS

Voltage Control

PIN 1

PIN 2

PIN 3

PIN 4

PIN 5

PIN 6

Enable/Disable

or N/C

Ground

Output

Comp. Output

or N/C

Voltage Supply

.90

Dimension Units: mm

Part Number Guide

Package

Input

Voltage

3 = 3.3V

6 = 2.5V

Sample Part Number:

Stability

(in ppm)

F =

20

A =

25

B =

50

I642–31AB9H2–155.520

Enable / Disable

(Pin 2)

H = Enable

O = N/C

Operating

Temperature

1 = 0 C to +70 C

2 = -40 C to +85 C

3 = -20 C to +70 C

Pullabilty

B =



C =

100

Output

3 = LVCMOS

8 = LVDS

9 = LVPECL

Complimentary

Ouput (Pin 5) **

1 = N.C.

2 = Output

Frequency

I642

-155.520 MHz

NOTE: A 0.01 µF bypass capacitor is recommended between V

(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of

waveform. ** Available on LVDS and LVPECL ouput only

ILSI America Phone 775-851-8880

●

Fax 775-851-8882

●email:

e-mail@ilsiamerica.com

●

www.ilsiamerica.com

Specifications subject to change without notice

Rev: 03/10/15_A

Page 1 of 3

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