Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mount applications.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and in
automotive and general purpose
switching applications.
BUK565-100A
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V
GS
= 5 V
MAX.
100
25
125
175
0.085
UNIT
V
A
W
˚C
Ω
PINNING - SOT404
PIN
1
2
3
mb
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
t
p
≤
50
µs
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
MAX.
100
100
15
20
25
18
100
125
175
175
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
minimum footprint,
FR4 board (see Fig 18).
-
TYP. MAX.
-
50
1.2
-
UNIT
K/W
K/W
February 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
STATIC CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
DSS
I
GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
V
DS
= V
GS
; I
D
= 1 mA
V
DS
= 100 V; V
GS
= 0 V; T
j
= 25 ˚C
V
DS
= 100 V; V
GS
= 0 V; T
j
=125 ˚C
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 13 A
MIN.
100
1.0
-
-
-
-
BUK565-100A
TYP.
-
1.5
1
0.1
10
0.075
MAX.
-
2.0
10
1.0
100
0.085
UNIT
V
V
µA
mA
nA
Ω
DYNAMIC CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
s
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 13 A
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
V
DD
= 30 V; I
D
= 3 A;
V
GS
= 5 V; R
GS
= 50
Ω;
R
gen
= 50
Ω
Measured from upper edge of drain
tab to centre of die
Measured from source lead
soldering point to source bond pad
MIN.
10
-
-
-
-
-
-
-
-
-
TYP.
13.5
1450
280
100
25
65
135
80
2.5
7.5
MAX.
-
1750
350
150
40
85
180
110
-
-
UNIT
S
pF
pF
pF
ns
ns
ns
ns
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
-
-
I
F
= 25 A ; V
GS
= 0 V
I
F
= 25 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 30 V
MIN.
-
-
-
-
-
TYP.
-
-
1.3
90
0.8
MAX.
25
100
1.7
-
-
UNIT
A
A
V
ns
µC
AVALANCHE LIMITING VALUE
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 25 A ; V
DD
≤
50 V ;
V
GS
= 5 V ; R
GS
= 50
Ω
MIN.
-
TYP.
-
MAX.
140
UNIT
mJ
February 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK565-100A
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
10
Zth j-mb / (K/W)
BUKx55-lv
1
D=
0.5
0.2
0.1
0.05
0.02
0
P
D
t
p
D=
t
p
T
t
1E+01
0.1
0.01
0
20
40
60
80 100
Tmb / C
120
140
160
180
0.001
1E-07
T
1E-05
1E-03
t/s
1E-01
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
ID%
Normalised Current Derating
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
ID / A
10
7
40
30
20
3
10
0
VGS / V =
4
5
BUK555-100A
120
110
100
90
80
70
60
50
40
30
20
10
0
50
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
2
4
VDS / V
6
8
10
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
ID / A
BUK555-100A,B
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON) / Ohm
VGS / V =
3
3.5
BUK555-100A
1000
0.5
0.4
2.5
100
S(
RD
)
ON
D
=V
S/
ID
A
tp = 10 us
100 us
0.3
0.2
0.1
4
4.5
5
10
10
DC
1 ms
10 ms
100 ms
1
1
10
VDS / V
100
1000
0
0
20
ID / A
40
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
February 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK565-100A
50
ID / A
Tj / C =
25
150
BUK555-100A
2
VGS(TO) / V
max.
40
typ.
30
1
min.
20
10
0
0
2
4
VGS / V
6
8
0
-60
-20
20
60
Tj / C
100
140
180
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
gfs / S
BUK555-100A
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
ID / A
SUB-THRESHOLD CONDUCTION
20
1E-01
1E-02
15
1E-03
2%
typ
98 %
10
1E-04
5
1E-05
0
0
20
ID / A
40
1E-06
0
0.4
0.8
1.2
VGS / V
1.6
2
2.4
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
a
Normalised RDS(ON) = f(Tj)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
C / pF
BUK5y5-100
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10000
1000
Ciss
Coss
100
Crss
-60
-20
20
60
Tj / C
100
140
180
10
0
20
VDS / V
40
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 13 A; V
GS
= 5 V
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
February 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK565-100A
12
10
8
6
4
2
0
VGS / V
BUK555-100
VDS / V =20
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
80
0
20
QG / nC
40
20
40
60
80
100
120
Tmb / C
140
160
180
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
IF / A
BUK555-100A
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 25 A
50
+
40
VDD
L
VDS
30
VGS
20
Tj / C = 150
10
25
-
-ID/100
T.U.T.
R 01
shunt
0
RGS
0
0
1
VSDS / V
2
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
February 1996
5
Rev 1.000
Microcontroller MCU
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