Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope using ’trench’
technology which features very low
on-state resistance. It is intended for
use in automotive and general
purpose switching applications.
BUK9505-30A
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
V
GS
= 10 V
MAX.
30
75
230
175
5
4.6
UNIT
V
A
W
˚C
mΩ
mΩ
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
source
drain
1 23
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
t
p
≤50µS
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
30
30
10
15
75
75
400
230
175
UNIT
V
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
in free air
TYP.
-
60
MAX.
0.65
-
UNIT
K/W
K/W
August 1999
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 30 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
V
GS
= 4.5 V; I
D
= 25 A
T
j
= 175˚C
T
j
= 175˚C
MIN.
30
27
1
0.5
-
-
-
-
-
-
-
-
BUK9505-30A
TYP.
-
-
1.5
-
-
0.05
-
2
4.3
-
3.9
-
MAX.
-
-
2.0
-
2.3
10
500
100
5
9.3
4.6
5.4
UNIT
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
PARAMETER
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
-
-
-
-
-
-
-
-
-
-
TYP.
6500
1500
1000
45
220
435
320
3.5
4.5
7.5
MAX.
8600
1800
1350
65
330
600
450
-
-
-
UNIT
pF
pF
pF
ns
ns
ns
ns
nH
nH
nH
V
DD
= 30 V; R
load
=1.2Ω;
V
GS
= 5 V; R
G
= 10
Ω
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 75 A; V
GS
= 0 V
I
F
= 75 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.85
1.1
400
1.0
MAX.
75
240
1.2
-
-
-
UNIT
A
A
V
V
ns
µC
August 1999
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 75 A; V
DD
≤
25 V;
V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
BUK9505-30A
TYP.
-
MAX.
500
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID/A
RDS(ON) = VDS/ID
100
tp =
100uS
1mS
10mS
10
DC
100mS
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
1
10
VDS/V
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
ID%
Normalised Current Derating
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
1
D=
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0
Zth / (K/W)
P
D
t
p
D=
t
p
T
t
T
0
20
40
60
80 100
Tmb / C
120
140
160
180
0.001
0.00001
0.001
t/S
0.1
10
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
August 1999
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9505-30A
10.0
7.0
ID/V 6.0
5.0
300
400
4.8
4.6
4.4
100
VGS/V =
4.2
4.0
3.8
3.6
ID/A
80
60
Tj/C =
40
175
25
200
3.4
3.2
3.0
2.8
2.6
2.4
100
20
0
0
0
2
4
VDS/V
6
8
10
0
0.5
1
1.5
VGS/V
2
2.5
3
3.5
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
150
gfs/S
11
10
9
VGS/V =
8
7
6
5
4
3
0
3.0
3.2
3.4
3.6
4.0
5.0
100
50
20
40
ID/A
60
80
100
0
0
20
40
ID/A
60
80
100
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
RDS(ON)/mOhm
Fig.9. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
a
2
6.5
6
5.5
5
30V TrenchMOS
1.5
1
4.5
4
3.5
3
0.5
3
4
5
6 VGS/V 7
8
9
10
0
-100
-50
0
50
Tj / C
100
150
200
Fig.7. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
GS
); conditions: I
D
= 25 A;
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
August 1999
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9505-30A
2.5
VGS(TO) / V
max.
BUK959-60
6
VGS/V
5
2
typ.
1.5
min.
1
2
3
4
VDS =
14V
24V
0.5
1
0
-100
-50
0
50
Tj / C
100
150
200
0
0
20
40
60
QG/nC
80
100
120
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
100
ID/A
80
1E-01
1E-02
2%
typ
98%
60
Tj/C =
40
175
25
1E-03
1E-04
20
1E-05
0
1E-05
0
0.1
0.2
0.3
0.4
0.5
0
0.5
1
1.5
2
2.5
3
0.6 0.7
VSDS/V
0.8
0.9
1
1.1
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
20
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
120
110
100
15
90
80
70
Thousands pF
10
60
50
40
Ciss
5
30
20
10
0
0.01
0.1
1
VDS/V
10
Coss
Crss
100
0
20
40
60
80
100
120
Tmb / C
140
160
180
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
August 1999
5
Rev 1.100
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