Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
DESCRIPTION
The Philips 8XC451 is an I/O expanded single-chip microcontroller
fabricated with Philips high-density CMOS technology. Philips
epitaxial substrate minimizes latch-up sensitivity.
The 8XC451 (includes the 80C451, 87C451 and 83C451) is a
functional extension of the 87C51 microcontroller with three
additional I/O ports and four I/O control lines for a total of 68 pins.
Four control lines associated with port 6 facilitate high-speed
asynchronous I/O functions.
The 8XC451 includes a 4k
×
8 ROM (83C451) EPROM (87C451), a
128
×
8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two
priority level, nested interrupt structure, a serial I/O port for either a
full duplex UART, I/O expansion, or multi-processor
communications, and on-chip oscillator and clock circuits. The
80C451 ROMless version includes all of the 83C451 features except
the on-board 4k
×
8 ROM.
The 87C451 has 4k of EPROM on-chip as program memory and is
otherwise identical to the 83C451.
The 8XC451 has two software selectable modes of reduced activity
for further power reduction; idle mode and power-down mode. Idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. Power-down mode
freezes the oscillator, causing all other chip functions to be
inoperative while maintaining the RAM contents.
PIN CONFIGURATION
9
1
61
10
60
LCC
26
44
27
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Function
EA/V
PP
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
CC
P4.7
P4.6
P4.5
P4.4
P4.3
Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Function
P4.2
P4.1
P4.0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
P5.0
P5.1
P5.2
43
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
P5.3
P5.4
P5.5
P5.6
P5.7
XTAL2
XTAL1
V
SS
ODS
IDS
BFLAG
AFLAG
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
PSEN
ALE/PROG
FEATURES
•
80C51 based architecture
•
Seven 8-bit I/O ports
•
Port 6 features:
– Eight data pins
– Four control pins
– Direct MPU bus interface
– Parallel printer interface
SU00084A
•
On the microcontroller:
– 4k
×
8 ROM (83C451)
4k
×
8 EPROM (87C451)
ROMless version (80C451)
– 128
×
8 RAM
– Two 16-bit counter/timers
– Two external interrupts
•
External memory addressing capability
– 64k ROM and 64k RAM
•
Low power consumption:
– Normal operation: less than 24mA at 5V, 12MHz
– Idle mode
– Power-down mode
1998 May 01
2
853-0830 19327
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
PIN DESCRIPTION
MNEMONIC
V
SS
V
CC
P0.0–0.7
PIN
NO.
54
18
17-10
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order
address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and
drive CMOS inputs without external pull-ups.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS
TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions
listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Port 4:
Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
Port 5:
Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
Port 6:
Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in
a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that
serve the functions listed below:
ODS:
Output data strobe
IDS:
Input data strobe
BFLAG:
Bidirectional I/O pin with internal pull-ups
AFLAG:
Bidirectional I/O pin with internal pull-ups
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to V
CC
.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of the address during
an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except
during an external data memory access, at which time one ALE is skipped. ALE can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse
during EPROM programming.
Program Store Enable:
The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program
memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source
eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low
during programming.
Instruction Execution Control/Programming Supply Voltage:
When EA is held high, the CPU
executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is
held low, the CPU executes out of external program memory. EA must never be allowed to float. This
pin also receives the 12.75V programming supply voltage (V
PP
) during EPROM programming.
Crystal 1:
Input to the inverting oscillator amplifier that forms the oscillator. This input receives the
external oscillator when an external oscillator is used.
Crystal 2:
An output of the inverting amplifier that forms the oscillator. This pin should be floated when
an external oscillator is used.
P1.0–P1.7
27-34
I/O
P2.0–P2.7
2-9
I/O
P3.0–P3.7
36-43
I/O
36
37
38
39
40
41
42
43
P4.0–P4.7
P5.0–P5.7
P6.0–P6.7
26-19
44-51
59-66
I
O
I
I
I
I
O
O
I/O
I/O
I/O
ODS
IDS
BFLAG
AFLAG
RST
ALE/PROG
55
56
57
58
35
68
I
I
I/O
I/O
I
I/O
PSEN
67
O
EA/V
PP
1
I
XTAL1
XTAL2
53
52
I
O
1998 May 01
5
Real-time operating system RTOS
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