SC3200UFH-266F datasheet, PDF - EEWORLD Datasheet

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SC3200UFH-266F: DescriptionAMD GEODE-TM SC3200 PROCESSOR; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，447 Pages; ManufacturerAMD; Websitehttp://www.amd.com; Environmental Compliance

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SC3200UFH-266F Overview

AMD GEODE-TM SC3200 PROCESSOR

SC3200UFH-266F Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	AMD
Parts packaging code	BGA
package instruction	LEAD FREE, MS-034BAU-1, TEBGA-481
Contacts	481
Reach Compliance Code	unknow
ECCN code	3A991.A.2
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	27 MHz
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B481
JESD-609 code	e2
length	40 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	481
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA481,31X31,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.59 mm
speed	266 MHz
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver (Sn96.5Ag3.5)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	40 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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AMD Geode™ SC3200 Processor

Data Book

March 2004

Publication ID: Revision 5.1

AMD Geode™ SC3200 Processor Data Book

Contents

Revision 5.1

Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.0

AMD Geode™ SC3200 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1

1.2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.0

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1

2.2

2.3

2.4

2.5

GX1 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Video Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Super I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock, Timers, and Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.0

Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1

3.2

3.3

3.4

Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Multiplexing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.0

General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.1

4.2

4.3

4.4

4.5

Configuration Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Multiplexing, Interrupt Selection, and Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . 88

WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

High-Resolution Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Clock Generators and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.0

SuperI/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Configuration Structure / Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Standard Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

System Wakeup Control (SWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Legacy Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

AMD Geode™ SC3200 Processor Data Book

Revision 5.1

Contents

6.0

Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

6.1

6.2

6.3

6.4

Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Chipset Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.0

Video Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

7.1

7.2

7.3

Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

8.0

9.0

Debugging and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

8.1

Testability (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

9.1

9.2

9.3

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

10.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

10.1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

10.2 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Appendix A

A.1

A.2

Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

AMD Geode™ SC3200 Processor Data Book

List of Figures

Revision 5.1

List of Figures

Figure 1-1.

Figure 3-1.

Figure 3-2.

Figure 3-3.

Figure 4-1.

Figure 4-2.

Figure 4-3.

Figure 5-1.

Figure 5-2.

Figure 5-3.

Figure 5-4.

Figure 5-5.

Figure 5-6.

Figure 5-7.

Figure 5-8.

Figure 5-9.

Figure 5-10.

Figure 5-11.

Figure 5-12.

Figure 5-13.

Figure 5-14.

Figure 5-15.

Figure 5-16.

Figure 5-17.

Figure 5-18.

Figure 5-19.

Figure 6-1.

Figure 6-2.

Figure 6-3.

Figure 6-4.

Figure 6-5.

Figure 6-6.

Figure 6-7.

Figure 6-8.

Figure 6-9.

Figure 6-10.

Figure 6-11.

Figure 6-12.

Figure 6-13.

Figure 6-14.

Figure 6-15.

Figure 7-1.

Figure 7-2.

Figure 7-3.

Figure 7-4.

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

432-EBGA Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

481-TEPBGA Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

WATCHDOG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Recommended Oscillator External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Detailed SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Structure of the Standard Configuration Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Standard Configuration Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Recommended Oscillator External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Divider Chain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Typical Battery Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Typical Battery Current: Battery Backed Power Mode @ T

= 25°C . . . . . . . . . . . . . . . . . 124

Typical Battery Current: Normal Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Interrupt/Status Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

ACCESS.bus Data Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

ACCESS.bus Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

A Complete ACCESS.bus Data Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

UART Mode Register Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

IRCP/SP3 Register Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Core Logic Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Non-Posted Fast-PCI to ISA Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

PCI to ISA Cycles with Delayed Transaction Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

ISA DMA Read from PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

ISA DMA Write to PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

PCI Change to Sub-ISA and Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

PIT Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

PIC Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

PCI and IRQ Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

General Purpose Timer and UDEF Trap SMI Tree Example . . . . . . . . . . . . . . . . . . . . . . . . 181

PRD Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

AC97 V2.0 Codec Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Audio SMI Tree Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Typical Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

NTSC 525 Lines, 60 Hz, Odd Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

NTSC 525 Lines, 60 Hz, Even Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

VIP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

AMD Geode™ SC3200 Processor Data Book

SC3200UFH-266F Related Products

	SC3200UFH-266F	SC3200	SC3200UCL-266F	SC3200UCL-266	SC3200UFH-233	SC3200UFH-266	SC3200UFH-233F
Description	AMD GEODE-TM SC3200 PROCESSOR	AMD GEODE-TM SC3200 PROCESSOR	AMD GEODE-TM SC3200 PROCESSOR	AMD GEODE-TM SC3200 PROCESSOR	AMD GEODE-TM SC3200 PROCESSOR	AMD GEODE-TM SC3200 PROCESSOR	AMD GEODE-TM SC3200 PROCESSOR
Is it Rohs certified?	conform to	-	conform to	incompatible	incompatible	incompatible	conform to
Maker	AMD	-	AMD	AMD	AMD	AMD	AMD
Parts packaging code	BGA	-	BGA	BGA	BGA	BGA	BGA
package instruction	LEAD FREE, MS-034BAU-1, TEBGA-481	-	BGA, BGA432,31X31,50	BGA, BGA432,31X31,50	40 X 40 MM, 2.38 MM HEIGHT, 1.27 MM PITCH, PLASTIC, MS-034BAU-1, TEBGA-481	40 X 40 MM, 2.38 MM HEIGHT, 1.27 MM PITCH, PLASTIC, MS-034BAU-1, TEBGA-481	LEAD FREE, MS-034BAU-1, TEBGA-481
Contacts	481	-	432	432	481	481	481
Reach Compliance Code	unknow	-	compli	compli	_compli	_compli	unknow
ECCN code	3A991.A.2	-	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2
Address bus width	32	-	13	13	13	13	32
bit size	32	-	32	32	32	32	32
boundary scan	YES	-	YES	YES	YES	YES	YES
maximum clock frequency	27 MHz	-	27 MHz	27 MHz	27 MHz	27 MHz	27 MHz
External data bus width	64	-	64	64	64	64	64
Format	FIXED POINT	-	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FIXED POINT
Integrated cache	YES	-	YES	YES	YES	YES	YES
JESD-30 code	S-PBGA-B481	-	S-PBGA-B432	S-PBGA-B432	S-PBGA-B481	S-PBGA-B481	S-PBGA-B481
JESD-609 code	e2	-	e1	e0	e0	e0	e2
length	40 mm	-	40 mm	40 mm	40 mm	40 mm	40 mm
low power mode	YES	-	YES	YES	YES	YES	YES
Humidity sensitivity level	3	-	-	-	3	3	3
Number of terminals	481	-	432	432	481	481	481
Maximum operating temperature	85 °C	-	85 °C	85 °C	85 °C	85 °C	85 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	-	BGA	BGA	HBGA	HBGA	BGA
Encapsulate equivalent code	BGA481,31X31,50	-	BGA432,31X31,50	BGA432,31X31,50	BGA481,31X31,50	BGA481,31X31,50	BGA481,31X31,50
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.8,3.3 V	-	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.59 mm	-	1.75 mm	1.75 mm	2.59 mm	2.59 mm	2.59 mm
speed	266 MHz	-	266 MHz	266 MHz	233 MHz	266 MHz	233 MHz
Maximum supply voltage	1.89 V	-	1.89 V	1.89 V	1.89 V	1.89 V	1.89 V
Minimum supply voltage	1.71 V	-	1.71 V	1.71 V	1.71 V	1.71 V	1.71 V
Nominal supply voltage	1.8 V	-	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	-	YES	YES	YES	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	-	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Silver (Sn96.5Ag3.5)	-	TIN SILVER COPPER	Tin/Lead (Sn/Pb)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Silver (Sn96.5Ag3.5)
Terminal form	BALL	-	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	40 mm	-	40 mm	40 mm	40 mm	40 mm	40 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	-	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR

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