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• Organization: 512Kx8/256Kx16
• Sector architecture
- One 16K; two 8K; one 32K; and seven 64K byte sectors
- One 8K; two 4K; one 16K; and seven 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• Hardware
RE S E T
pin
- Resets internal state machine to read mode
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
• Detection of program/erase cycle completion
- DQ7
DATA
polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/
BY
output
• Erase suspend/resume
- Supports reading data from or programming data
to a sector not being erased
• Low V
CC
write lock-out below 1.5V
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
DQ0–DQ15
/RJLF EORFN GLDJUDP
RY/BY
V
CC
V
SS
Sector protect/
erase voltage
switches
Erase voltage
generator
RESET
WE
BYTE
Command
register
Program/erase
control
Input/output
buffers
Program voltage
generator
Chip enable
Output enable
Logic
STB
Data latch
CE
OE
A-1
V
CC
detector
Timer
Address latch
STB
Y decoder
Y gating
X decoder
Cell matrix
A0–A17
6HOHFWLRQ JXLGH
Maximum access time
Maximum chip enable access time
Maximum output enable access time
t
AA
t
CE
t
OE
29LV400-70
70
70
30
29LV400-80
80
80
30
29LV400-90
90
90
35
29LV400-120
120
120
50
Unit
ns
ns
ns
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48-pin TSOP
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
OE
V
SS
CE
A0
BY
/RY
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
AS29LV400
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
AS29LV400
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
44-pin SO (availability TBD)
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
DQ0
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
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The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible
Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k
byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears
on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP and 44-pin SO. This device is designed to be
programmed and erased with a single 3.0V V
CC
supply. The device can also be reprogrammed in standard EPROM programmers.
The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable
(C E )
, write enable
(WE )
, and output enable
(O E )
controls. Word
mode (×16 output) is selected by
B YT E
= high. Byte mode (×8 output) is selected by
BY TE
= low.
The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor
write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and
programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations.
Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip
programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase
command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already
programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper
cell margins.
Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the
Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend,
which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip
Erase command will automatically erase all unprotected sectors.
When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is
programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change
bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no
effect on other sectors.
The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and
regulated voltages are provided for the Program and Erase operations. A low V
CC
detector automatically inhibits write operations
during power transtitions. The
RY/BY
pin,
DATA
polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the
program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are
completed. DQ2 indicates which sectors are being erased.
The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control
register architecture permits alteration of memory contents only when successful completion of specific command sequences has
occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if V
CC
is less than V
LKO
(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on
O E , CE , or WE
. To initiate Write
commands,
CE
and
WE
must be a logical zero and
O E
a logical 1.
When the device’s hardware
R E S E T
pin is driven low, any Program/Erase operation in progress is terminated and the internal
state machine is reset to Read mode. If the
RE S E T
pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require
rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.
The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using the EPROM programming mechanism of hot electron injection.
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Mode
ID read MFR code
ID read device code
Read
Standby
Output disable
Write
Enable sector protect
Sector unprotect
Temporary sector
unprotect
Verify sector protect
†
Verify sector unprotect
†
Hardware Reset
CE
OE
WE
L
L
L
H
L
L
L
L
X
L
L
X
L
L
L
X
H
H
V
ID
V
ID
X
L
L
X
H
H
H
X
H
L
Pulse/L
Pulse/L
X
H
H
X
A0
L
H
A0
X
X
A0
L
L
X
L
L
X
A1
L
L
A1
X
X
A1
H
H
X
H
H
X
A6
L
L
A6
X
X
A6
L
H
X
L
H
X
A9
V
ID
V
ID
A9
X
X
A9
V
ID
V
ID
X
V
ID
V
ID
X
R E SE T
DQ
Code
Code
D
OUT
High Z
High Z
D
IN
X
X
X
Code
Code
High Z
H
H
H
H
H
H
H
H
V
ID
H
H
L
L = Low (<V
IL
) = logic 0; H = High (>V
IH
) = logic 1; V
ID
= 10.0 ± 1.0V; X = don’t care.
In ×16 mode, BYTE = V
IH
. In ×8 mode, BYTE = V
IL
with DQ8-DQ14 in high Z and DQ15 = A-1.
†
Verification of sector protect/unprotect during A9 = V
ID.
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Description
Selected by A9 = V
ID
(9.5V–10.5V),
C E
=
O E
= A1 = A6 = L, enabling outputs.
ID MFR code,
When A0 is low (V
IL
) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
device code
When A0 is high (V
IH
), D
OUT
represents the device code for the AS29LV400.
Selected with
CE
=
O E
= L,
WE
= H. Data is valid in t
ACC
time after addresses are stable, t
CE
after
C E
is low
Read mode
and t
OE
after
O E
is low.
Selected with
C E
= H. Part is powered down, and I
CC
reduced to <1.0 µA when
C E
= V
CC
± 0.3V =
RE S E T
.
If activated during an automated on-chip algorithm, the device completes the operation before entering
Standby
standby.
Output disable Part remains powered up; but outputs disabled with
O E
pulled high.
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
Write
on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Hardware protection circuitry implemented with external programming equipment causes the device to
Enable
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
sector protect
protect algorithm on page 12.
Disables sector protection for all sectors using external programming equipment. All sectors must be
Sector
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect
unprotect
algorithm on page 12.
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
Verify sector
programming equipment. Determine if sector protection exists in a system by writing the ID read command
protect/
sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A
unprotect
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to
R ES E T
Temporary
to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected
sector
sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal
unprotect
of +10V from
R ES E T
.
Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
RE SE T
may be corrupted.
Deep
Hold RESET low to enter deep power down mode (
<
1 µA). Recovery time to start of first read cycle is 50ns.
power down
Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is
Automatic
available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new
sleep mode
data is returned within standard access times.
Item
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