SAA8122A
Digital Still Camera Processor (ImagIC family)
Rev. 01 — 20 April 2000
Objective specification
1. Description
The DSC SAA8122A is a high performance, low power, single-chip Million
Instructions Per Second (MIPS) based signal processor, part of the ImagIC family,
which is dedicated to image processing, compression, formatting and storage. The
DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022,
2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy
implementation of a complete system solution and fast development of high
performance consumer digital still cameras.
The SAA8122A is designed as a single-chip device, able to perform all treatments
and connections required for a wide range of Digital Still Cameras. Its embedded
RISC CPU, for which the development environment is available, enables shorter
development and validation cycles, as well as faster feature upgrade. Since one of
the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a
DSP (with advanced embedded algorithm) for camera signal processing is integrated
with a high level of programmability for pulses generation.
The JPEG core is hardware based in order to allow high-speed image data
compression.
2. Features
c
c
2.1 General
s
Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA),
with RGB Bayer filters up to 2 Mpixels
s
Performs an advanced RGB to YUV conversion
s
Includes a smart measurement unit to speed up the control loop (focus, auto white
balance, etc.)
s
Supports a wide range of LCD and TV formats (both NTSC and PAL) with text
insertion features
s
Includes an embedded JPEG encoder/decoder unit
s
Includes a MIPS PR3001 CPU, running at a frequency in a range from
12 to 28 MHz
s
PRISC compatible PI-bus architecture, interrupt, power management, clock and
reset architectures
s
Includes a dedicated video bus supporting SDRAM memory for picture storage
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
s
Interface to ROM, DRAM, SRAM, flash and PC Card [Compact Flash and SSFDC
(SmartMedia)]
s
Integrated general purpose peripheral units like a UART, timers, an I
2
C-bus
transceiver, ADC converters, RTC and I/O ports
s
Includes USB and RS-232C communication interfaces.
2.2 External interfaces
s
Two UART (RS-232) data ports with DMA capabilities (≤187.5 kbit/s) including
hardware flow control RxD, TxD, RTS, CTS for modem support
s
32 general purpose, bidirectional I/O interface pins, the first 8 bits may also be
used as interrupt inputs
s
Two PWM outputs (8-bit resolution).
2.3 CPU related features
s
s
s
s
s
s
s
s
32-bit PR3001 core
1-kbyte data cache and 4-kbyte instruction cache
Programmable low-power mode, including wake-up on interrupt
Memory management unit [Translation Lookaside Buffer (TLB)]
Two built in 24-bit general purpose timers and one 24-bit watchdog timer
Real-time clock unit (active in sleep mode)
On-chip 8-kbyte SRAM for storing code which needs fast execution
Platform software based on real-time pSOS (plug-in Silicon Operating System).
2.4 DSP features
s
Advanced colour reconstruction
s
Programmable digital filters for noise reduction and contour enhancement
s
16 programmable measurement windows allowing to perform the measurements
necessary for exposure, white balance and focus adjustment in a DSC system;
available measurement outputs for exposure, white balance and focus control.
2.5 Pulse pattern generator features
s
Programmable through dedicated PC-software, allowing to drive all CCDs
currently present in the market, as well as CDS/AGC/ADC chips: up to
8
×
8 kpixels.
2.6 JPEG
s
Fully ISO10918 compliant
s
Supports Tiff, Exif 2.1, DCF & DPOF
s
Quick compression (4 images/s for a 1.3 Mpixels resolution).
2.7 USB interface
s
Fully compatible with USB.
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
2 of 26
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
2.8 Card interfaces
s
Compatible with all SSFDC/CF cards on the market.
2.9 Bus
s
Bus structure allows for parallel processing depending on software
implementation, allowing easy system optimization.
2.10 SDRAM interface features
s
Supports up to 128 Mbyte of SDRAM and 16-bit wide addressses
s
Bus speed: 1 or 2 times CCD pixel clock
s
32-bit bus width.
3. Quick reference data
Table 1:
Symbol
V
DDD
V
DDA
I
P
V
I
Quick reference data
Parameter
digital supply voltage
analog supply current
total supply current
input voltage
general
5 V tolerant cells only
V
O
T
amb
f
clk
[1]
[2]
[3]
[3]
Conditions
[1]
[2]
Min
3
3
−
0
0
0
0
−
Typ
3.3
3.3
360
−
−
−
25
25
Max
3.6
3.6
560
V
DDD
5.5
V
DDD
70
27
Unit
V
V
mA
V
V
V
°C
MHz
f
clk
= 25 MHz
output voltage
ambient temperature
clock frequency
output active
The supplies considered as digital supply (V
DDD
) are: V
DDD
, V
DDD(RTC)
.
The supplies considered as analog supply (V
DDA
) are: V
DDA(SPLL)
, V
DDA(PLL)
, V
DDA(BG)
, V
DDA(PPG1)
,
V
DDA(ADC)
, V
DDA(OUTPUT1)
, V
DDA(OUTPUT2)
, V
DDA(LCDR)
, V
DDA(LCDG)
, V
DDA(LCDB)
, V
DDA(DLL)
.
Including voltage on outputs in 3-state mode; only valid when supply voltage is present.
4. Ordering information
Table 2:
Ordering information
Package
Name
SAA8122AEL
LFBGA324
Description
plastic low profile fine-pitch ball grid array package; 324 balls;
body 16
×
16
×
1.2 mm
Version
SOT571-1
Type number
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
3 of 26
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
9397 750 07048
Objective specification
TCB
PC-CARD
CONTROLLER
DRAM
MEMORY
CONTROLLER
PERIPHERAL
CONTROLLER
STATIC
MEMORY
CONTROLLER
JPEG
CODEC
EBIU
PR3001
CPU
INTERUPT
CONTROLLER
PLL
CCD
PI
BCU
5. Block diagram
Philips Semiconductors
INTERUPT
CONTROLLER
USB
UART
SAA8122A
SLAVE GROUP INTERFACE
Rev. 01 — 20 April 2000
TIMER
TIMER
I
2
C
TRANSCIEVER
GPIO
+
INT
FOUR
GPIO
RTC
POWER
MANAGEMENT
CONTROLLER
VDO
BCU
CAMDSP
8K
SRAM
TIMER
ANALOG
DIGITAL
CONTROLLER
FCE686
© Philips Electronics N.V. 2000. All rights reserved.
SAA8122A
Digital Still Camera Processor (ImagIC family)
4 of 26
Fig 1. Block diagram.
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
handbook, full pagewidth
to LCD
to TV
lens
CCD
FXA1022
10
TDA9952
to cards
(SSFDC, CF)
SAA8122A
V-DRIVER
TDA9991
USB
IRDA
to PC
FCE687
Fig 2. System block diagram.
6. Pinning information
6.1 Pinning
handbook, halfpage
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FCE677
SAA8122AEL
Fig 3. Pin configuration (bottom view).
6.2 Pin description
Table 3:
Symbol
V
DDD
V
SSA(DLL)
V
DDA(DLL)
DISP_VSYNC
IO1/IRQ17
V
DDA(LCDG)
V
DDA(OUTPUT2)
9397 750 07048
Pin description
Pin
A1
A2
A3
A4
A5
A6
A7
Type
-
-
-
O
I/O
P
P
Description
digital supply voltage
analog ground for DLL of PPG
analog supply voltage for DLL of PPG
digital vertical synchronization signal
I/O port 0 bit 1 or interrupt request 17
analog supply voltage for DAC component G
analog supply voltage for DAC video output 2
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
5 of 26
京公网安备 11010802033920号
EEWORLD
